Add ISX iM1283 board
ISX iM1283 is a "simple eDP signal generator" which utilizes a XC7A100T FPGA, and come with a header populated with the FPGA's JTAG. This commit adds initial reverse engineered IOs including the DDR3 DRAM (which cannot work reliably @ DDR3-800, so the system clock is defaultly set to 80MHz now), two LEDs and SD slot. Signed-off-by: Icenowy Zheng <uwu@icenowy.me>
This commit is contained in:
Icenowy Zheng
parent
3b339ba9a3
commit
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#
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# This file is part of LiteX-Boards.
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#
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# Copyright (c) 2021 Icenowy Zheng <icenowy@aosc.io>
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# Copyright (c) 2015 Yann Sionneau <yann.sionneau@gmail.com>
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# Copyright (c) 2015-2019 Florent Kermarrec <florent@enjoy-digital.fr>
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# SPDX-License-Identifier: BSD-2-Clause
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from litex.build.generic_platform import *
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from litex.build.xilinx import XilinxPlatform, VivadoProgrammer
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from litex.build.openocd import OpenOCD
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# IOs ----------------------------------------------------------------------------------------------
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_io = [
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# Clk / Rst
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("clk200", 0,
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Subsignal("p", Pins("E5"), IOStandard("LVDS_25")),
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Subsignal("n", Pins("D5"), IOStandard("LVDS_25")),
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),
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# Leds
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("user_led", 0, Pins("A22"), IOStandard("LVCMOS33")),
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("user_led", 1, Pins("C22"), IOStandard("LVCMOS33")),
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# Switches
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("sw", 0, Pins("C23"), IOStandard("LVCMOS33")),
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("sw", 1, Pins("B25"), IOStandard("LVCMOS33")),
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("sw", 2, Pins("A25"), IOStandard("LVCMOS33")),
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("sw", 3, Pins("A23"), IOStandard("LVCMOS33")),
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# Serial
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("serial", 0,
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Subsignal("tx", Pins("G24")),
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Subsignal("rx", Pins("F24")),
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IOStandard("LVCMOS33")
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),
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# SPIFlash
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("spiflash", 0,
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Subsignal("cs_n", Pins("P18")),
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Subsignal("clk", Pins("H13")),
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Subsignal("mosi", Pins("R14")),
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Subsignal("miso", Pins("R15")),
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Subsignal("wp", Pins("P14")),
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Subsignal("hold", Pins("N14")),
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IOStandard("LVCMOS33"),
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),
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("spiflash4x", 0,
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Subsignal("cs_n", Pins("P18")),
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Subsignal("clk", Pins("H13")),
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Subsignal("dq", Pins("R14 R15 P14 N14")),
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IOStandard("LVCMOS33")
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),
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# DDR3 SDRAM
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("ddram", 0,
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Subsignal("a", Pins(
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"D4 D3 C2 E3 B2 A2 A5 A4 B5 C3",
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"F2 A3 D1 C4 B4"),
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IOStandard("SSTL15")),
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Subsignal("ba", Pins("G4 F4 F3"), IOStandard("SSTL15")),
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Subsignal("ras_n", Pins("G2"), IOStandard("SSTL15")),
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Subsignal("cas_n", Pins("G1"), IOStandard("SSTL15")),
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Subsignal("we_n", Pins("E2"), IOStandard("SSTL15")),
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Subsignal("cs_n", Pins("E1"), IOStandard("SSTL15")),
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Subsignal("dm", Pins(
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"U2 T5",
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"L7 K1"
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), IOStandard("SSTL15")),
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Subsignal("dq", Pins(
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"T2 T4 R2 P4 P3 N4 R3 T3",
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"P8 R6 T8 R5 R8 P6 T7 R7",
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"L5 M7 K3 N6 J3 N7 K5 M6",
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"L3 L2 K2 H2 M2 H1 N3 J1"
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),
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IOStandard("SSTL15"),
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Misc("IN_TERM=UNTUNED_SPLIT_40")),
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Subsignal("dqs_p", Pins(
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"R1 U6",
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"M4 N1"
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),
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IOStandard("DIFF_SSTL15"),
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Misc("IN_TERM=UNTUNED_SPLIT_40")),
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Subsignal("dqs_n", Pins(
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"P1 U5",
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"L4 M1"
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),
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IOStandard("DIFF_SSTL15"),
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Misc("IN_TERM=UNTUNED_SPLIT_40")),
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Subsignal("clk_p", Pins("C1"), IOStandard("DIFF_SSTL15")),
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Subsignal("clk_n", Pins("B1"), IOStandard("DIFF_SSTL15")),
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Subsignal("cke", Pins("J4"), IOStandard("SSTL15")),
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Subsignal("odt", Pins("H4"), IOStandard("SSTL15")),
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Subsignal("reset_n", Pins("N2"), IOStandard("SSTL15")),
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Misc("SLEW=FAST"),
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),
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## sdcard connector
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("spisdcard", 0,
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Subsignal("clk", Pins("P24")),
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Subsignal("mosi", Pins("R25"), Misc("PULLUP True")),
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Subsignal("cs_n", Pins("P25"), Misc("PULLUP True")),
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Subsignal("miso", Pins("N23"), Misc("PULLUP True")),
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Misc("SLEW=FAST"),
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IOStandard("LVCMOS33"),
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),
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("sdcard", 0,
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Subsignal("data", Pins("N23 M25 N26 P25"), Misc("PULLUP True")),
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Subsignal("cmd", Pins("R25"), Misc("PULLUP True")),
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Subsignal("clk", Pins("P24")),
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Subsignal("cd", Pins("M26"), Misc("PULLUP True")),
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Misc("SLEW=FAST"),
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IOStandard("LVCMOS33"),
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),
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]
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# Connectors ---------------------------------------------------------------------------------------
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_connectors = []
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# Platform -----------------------------------------------------------------------------------------
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class Platform(XilinxPlatform):
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default_clk_name = "clk200"
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default_clk_period = 1e9/200e6
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def __init__(self, toolchain="vivado"):
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XilinxPlatform.__init__(self, "xc7a100tfgg676-2", _io, _connectors, toolchain=toolchain)
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self.toolchain.bitstream_commands = \
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["set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 1 [current_design]"]
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self.toolchain.additional_commands = \
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["write_cfgmem -force -format bin -interface spix1 -size 16 "
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"-loadbit \"up 0x0 {build_name}.bit\" -file {build_name}.bin"]
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def create_programmer(self, name='vivado'):
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if name == 'vivado':
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return VivadoProgrammer()
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elif name == 'openocd':
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bscan_spi = "bscan_spi_xc7a100t.bit"
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return OpenOCD("openocd_xc7_ft2232.cfg", bscan_spi)
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def do_finalize(self, fragment):
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XilinxPlatform.do_finalize(self, fragment)
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self.add_period_constraint(self.lookup_request("clk200:p", loose=True), 1e9/200e6)
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@ -0,0 +1,114 @@
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#!/usr/bin/env python3
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#
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# This file is part of LiteX-Boards.
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#
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# Copyright (c) 2021 Icenowy Zheng <icenowy@aosc.io>
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# Copyright (c) 2020 Shinken Sanada <sanadashinken@gmail.com>
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# SPDX-License-Identifier: BSD-2-Clause
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import os
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import argparse
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from migen import *
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from litex_boards.platforms import isx_im1283
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from litex.build.xilinx.vivado import vivado_build_args, vivado_build_argdict
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from litex.soc.cores.clock import *
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from litex.soc.integration.soc_core import *
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from litex.soc.integration.builder import *
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from litex.soc.cores.led import LedChaser
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from litex.soc.cores.gpio import GPIOIn
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from litedram.modules import MT41J256M16
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from litedram.phy import s7ddrphy
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# CRG ----------------------------------------------------------------------------------------------
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class _CRG(Module):
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def __init__(self, platform, sys_clk_freq, with_video_pll=False, pix_clk=25.175e6):
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self.rst = Signal()
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self.clock_domains.cd_sys = ClockDomain()
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self.clock_domains.cd_sys4x = ClockDomain(reset_less=True)
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self.clock_domains.cd_sys4x_dqs = ClockDomain(reset_less=True)
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self.clock_domains.cd_idelay = ClockDomain()
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self.clock_domains.cd_hdmi = ClockDomain()
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self.clock_domains.cd_hdmi5x = ClockDomain()
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# # #
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self.submodules.pll = pll = S7PLL(speedgrade=-2)
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pll.register_clkin(platform.request("clk200"), 200e6)
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pll.create_clkout(self.cd_sys, sys_clk_freq)
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pll.create_clkout(self.cd_sys4x, 4*sys_clk_freq)
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pll.create_clkout(self.cd_sys4x_dqs, 4*sys_clk_freq, phase=90)
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pll.create_clkout(self.cd_idelay, 200e6)
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self.submodules.idelayctrl = S7IDELAYCTRL(self.cd_idelay)
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# BaseSoC ------------------------------------------------------------------------------------------
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class BaseSoC(SoCCore):
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def __init__(self, sys_clk_freq=int(80e6), with_led_chaser=True, **kwargs):
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platform = isx_im1283.Platform()
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# SoCCore ----------------------------------------------------------------------------------
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SoCCore.__init__(self, platform, sys_clk_freq,
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ident = "LiteX SoC on ISX iM1283",
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**kwargs)
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# CRG --------------------------------------------------------------------------------------
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self.submodules.crg = _CRG(platform, sys_clk_freq)
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# DDR3 SDRAM -------------------------------------------------------------------------------
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if not self.integrated_main_ram_size:
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self.submodules.ddrphy = s7ddrphy.A7DDRPHY(platform.request("ddram"),
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memtype = "DDR3",
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nphases = 4,
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sys_clk_freq = sys_clk_freq)
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self.add_sdram("sdram",
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phy = self.ddrphy,
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module = MT41J256M16(sys_clk_freq, "1:4"),
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l2_cache_size = kwargs.get("l2_size", 8192)
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)
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# Leds -------------------------------------------------------------------------------------
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if with_led_chaser:
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self.submodules.leds = LedChaser(
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pads = platform.request_all("user_led"),
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sys_clk_freq = sys_clk_freq)
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# Build --------------------------------------------------------------------------------------------
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def main():
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parser = argparse.ArgumentParser(description="LiteX SoC on iM1283")
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parser.add_argument("--build", action="store_true", help="Build bitstream")
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parser.add_argument("--load", action="store_true", help="Load bitstream")
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parser.add_argument("--sys-clk-freq", default=80e6, help="System clock frequency")
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sdopts = parser.add_mutually_exclusive_group()
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sdopts.add_argument("--with-spi-sdcard", action="store_true", help="Enable SPI-mode SDCard support")
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sdopts.add_argument("--with-sdcard", action="store_true", help="Enable SDCard support")
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builder_args(parser)
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soc_core_args(parser)
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vivado_build_args(parser)
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args = parser.parse_args()
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soc = BaseSoC(
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sys_clk_freq = int(float(args.sys_clk_freq)),
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**soc_core_argdict(args)
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)
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if args.with_spi_sdcard:
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soc.add_spi_sdcard()
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if args.with_sdcard:
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soc.add_sdcard()
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builder = Builder(soc, **builder_argdict(args))
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builder.build(**vivado_build_argdict(args), run=args.build)
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if args.load:
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prog = soc.platform.create_programmer()
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prog.load_bitstream(os.path.join(builder.gateware_dir, soc.build_name + ".bit"))
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if __name__ == "__main__":
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main()
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