Hardware
/
litex-boards
mirror of https://github.com/litex-hub/litex-boards.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

targets/Ultrascale+: use 500MHz IDELAYCTRL reference clock. 

The minimum is 300MHz on Ultrascale+ vs 200MHz on Ultrascale.
This commit is contained in:
Florent Kermarrec 2020-03-10 16:58:30 +01:00
parent e2a66090ee
commit 74a5ffb9ef
2 changed files with 10 additions and 10 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

10
litex_boards/targets/mercury_xu5.py
View File

@ -24,7 +24,7 @@ class _CRG(Module):
self.clock_domains.cd_sys = ClockDomain()
self.clock_domains.cd_sys4x = ClockDomain(reset_less=True)
self.clock_domains.cd_pll4x = ClockDomain(reset_less=True)
self.clock_domains.cd_clk200 = ClockDomain()
self.clock_domains.cd_clk500 = ClockDomain()
# # #
@ -32,7 +32,7 @@ class _CRG(Module):
pll.register_clkin(platform.request("clk100"), 100e6)
pll.create_clkout(self.cd_pll4x, sys_clk_freq*4, buf=None, with_reset=False)
pll.create_clkout(self.cd_clk200, 200e6, with_reset=False)
pll.create_clkout(self.cd_clk500, 500e6, with_reset=False)
self.specials += [
Instance("BUFGCE_DIV", name="main_bufgce_div",
@ -40,10 +40,10 @@ class _CRG(Module):
i_CE=1, i_I=self.cd_pll4x.clk, o_O=self.cd_sys.clk),
Instance("BUFGCE", name="main_bufgce",
i_CE=1, i_I=self.cd_pll4x.clk, o_O=self.cd_sys4x.clk),
AsyncResetSynchronizer(self.cd_clk200, ~pll.locked),
AsyncResetSynchronizer(self.cd_clk500, ~pll.locked),
]
self.submodules.idelayctrl = USIDELAYCTRL(cd_ref=self.cd_clk200, cd_sys=self.cd_sys)
self.submodules.idelayctrl = USIDELAYCTRL(cd_ref=self.cd_clk500, cd_sys=self.cd_sys)
# BaseSoC ------------------------------------------------------------------------------------------
@ -62,7 +62,7 @@ class BaseSoC(SoCSDRAM):
self.submodules.ddrphy = usddrphy.USPDDRPHY(platform.request("ddram"),
memtype = "DDR4",
sys_clk_freq = sys_clk_freq,
iodelay_clk_freq = 200e6,
iodelay_clk_freq = 500e6,
cmd_latency = 0)
self.add_csr("ddrphy")
self.add_constant("USDDRPHY", None)

10
litex_boards/targets/vcu118.py
View File

@ -24,7 +24,7 @@ class _CRG(Module):
self.clock_domains.cd_sys = ClockDomain()
self.clock_domains.cd_sys4x = ClockDomain(reset_less=True)
self.clock_domains.cd_pll4x = ClockDomain(reset_less=True)
self.clock_domains.cd_clk200 = ClockDomain()
self.clock_domains.cd_clk500 = ClockDomain()
# # #
@ -32,7 +32,7 @@ class _CRG(Module):
self.comb += pll.reset.eq(platform.request("cpu_reset"))
pll.register_clkin(platform.request("clk125"), 125e6)
pll.create_clkout(self.cd_pll4x, sys_clk_freq*4, buf=None, with_reset=False)
pll.create_clkout(self.cd_clk200, 200e6, with_reset=False)
pll.create_clkout(self.cd_clk500, 200e6, with_reset=False)
self.specials += [
Instance("BUFGCE_DIV", name="main_bufgce_div",
@ -40,10 +40,10 @@ class _CRG(Module):
i_CE=1, i_I=self.cd_pll4x.clk, o_O=self.cd_sys.clk),
Instance("BUFGCE", name="main_bufgce",
i_CE=1, i_I=self.cd_pll4x.clk, o_O=self.cd_sys4x.clk),
AsyncResetSynchronizer(self.cd_clk200, ~pll.locked),
AsyncResetSynchronizer(self.cd_clk500, ~pll.locked),
]
self.submodules.idelayctrl = USIDELAYCTRL(cd_ref=self.cd_clk200, cd_sys=self.cd_sys)
self.submodules.idelayctrl = USIDELAYCTRL(cd_ref=self.cd_clk500, cd_sys=self.cd_sys)
# BaseSoC ------------------------------------------------------------------------------------------
@ -62,7 +62,7 @@ class BaseSoC(SoCSDRAM):
self.submodules.ddrphy = usddrphy.USPDDRPHY(platform.request("ddram"),
memtype = "DDR4",
sys_clk_freq = sys_clk_freq,
iodelay_clk_freq = 200e6,
iodelay_clk_freq = 500e6,
cmd_latency = 0)
self.add_csr("ddrphy")
self.add_constant("USDDRPHY", None)