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nx_vip: Add missing 'origin' to SRAM SocRegions 

Signed-off-by: gatecat <gatecat@ds0.me>
This commit is contained in:
gatecat 2023-01-04 12:02:11 +01:00
parent f5643e7c78
commit 764f64ff1e
1 changed files with 4 additions and 2 deletions
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6
litex_boards/targets/lattice_crosslink_nx_vip.py
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@ -84,13 +84,15 @@ class BaseSoC(SoCCore):
# 128KB LRAM (used as SRAM) ------------------------------------------------------------ # 128KB LRAM (used as SRAM) ------------------------------------------------------------
size = 128*kB size = 128*kB
self.spram = NXLRAM(32, size) self.spram = NXLRAM(32, size)
self.bus.add_slave("sram", slave=self.spram.bus, region=SoCRegion(size=size)) self.bus.add_slave("sram", slave=self.spram.bus, region=SoCRegion(origin=self.mem_map["sram"],
size=size))
else: else:
# Use HyperRAM generic PHY as SRAM ----------------------------------------------------- # Use HyperRAM generic PHY as SRAM -----------------------------------------------------
size = 8*1024*kB size = 8*1024*kB
hr_pads = platform.request("hyperram", int(hyperram)) hr_pads = platform.request("hyperram", int(hyperram))
self.hyperram = HyperRAM(hr_pads, sys_clk_freq=sys_clk_freq) self.hyperram = HyperRAM(hr_pads, sys_clk_freq=sys_clk_freq)
self.bus.add_slave("sram", slave=self.hyperram.bus, region=SoCRegion(size=size)) self.bus.add_slave("sram", slave=self.hyperram.bus, region=SoCRegion(origin=self.mem_map["sram"],
size=size))
# Leds ------------------------------------------------------------------------------------- # Leds -------------------------------------------------------------------------------------
if with_led_chaser: if with_led_chaser: