rename forest_kitten_33 platform/target to fk33.
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parent
979fee7517
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@ -11,7 +11,7 @@ import argparse
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from migen import *
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from migen import *
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from litex_boards.platforms import forest_kitten_33
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from litex_boards.platforms import fk33
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from litex.soc.cores.clock import *
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from litex.soc.cores.clock import *
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from litex.soc.integration.soc_core import *
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from litex.soc.integration.soc_core import *
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@ -41,11 +41,11 @@ class _CRG(Module):
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class BaseSoC(SoCCore):
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class BaseSoC(SoCCore):
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def __init__(self, sys_clk_freq=int(125e6), with_pcie=False, **kwargs):
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def __init__(self, sys_clk_freq=int(125e6), with_pcie=False, **kwargs):
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platform = forest_kitten_33.Platform()
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platform = fk33.Platform()
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# SoCCore ----------------------------------------------------------------------------------
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# SoCCore ----------------------------------------------------------------------------------
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SoCCore.__init__(self, platform, sys_clk_freq,
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SoCCore.__init__(self, platform, sys_clk_freq,
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ident = "LiteX SoC on Forest Kitten 33",
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ident = "LiteX SoC on FK33",
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ident_version = True,
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ident_version = True,
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**kwargs)
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**kwargs)
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@ -99,7 +99,7 @@ class BaseSoC(SoCCore):
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# Build --------------------------------------------------------------------------------------------
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# Build --------------------------------------------------------------------------------------------
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def main():
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def main():
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parser = argparse.ArgumentParser(description="LiteX SoC on Forest Kitten 33")
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parser = argparse.ArgumentParser(description="LiteX SoC on FK33")
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parser.add_argument("--build", action="store_true", help="Build bitstream")
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parser.add_argument("--build", action="store_true", help="Build bitstream")
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parser.add_argument("--with-pcie", action="store_true", help="Enable PCIe support")
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parser.add_argument("--with-pcie", action="store_true", help="Enable PCIe support")
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parser.add_argument("--driver", action="store_true", help="Generate PCIe driver")
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parser.add_argument("--driver", action="store_true", help="Generate PCIe driver")
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