terasic_deca: Remove --integrated-ram-size parameter (--integrated-main-ram-size provides the same functionnality).
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@ -86,7 +86,6 @@ def main():
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parser.add_argument("--load", action="store_true", help="Load bitstream")
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parser.add_argument("--sys-clk-freq", default=50e6, help="System clock frequency (default: 50MHz)")
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parser.add_argument("--with-video-terminal", action="store_true", help="Enable Video Terminal (VGA)")
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parser.add_argument("--integrated-ram-size", default=0x4000, help="Use FPGA block RAM as main RAM. Interim measure until we have DDR3 support.")
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builder_args(parser)
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soc_core_args(parser)
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args = parser.parse_args()
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@ -94,7 +93,6 @@ def main():
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soc = BaseSoC(
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sys_clk_freq = int(float(args.sys_clk_freq)),
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with_video_terminal = args.with_video_terminal,
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integrated_main_ram_size = args.integrated_ram_size,
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**soc_core_argdict(args)
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)
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builder = Builder(soc, **builder_argdict(args))
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