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Allow building digilent_arty using f4pga 

Only use XADC() and DNA() functions if vivado is the current toolchain.
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Luc Lagarde 2023-01-06 16:09:56 -06:00 committed by GitHub
parent 6658f20682
commit 7a911b8ff6
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1 changed files with 5 additions and 3 deletions
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litex_boards/targets/digilent_arty.py
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@ -91,11 +91,13 @@ class BaseSoC(SoCCore):
SoCCore.__init__(self, platform, sys_clk_freq, ident="LiteX SoC on Arty A7", **kwargs)
# XADC -------------------------------------------------------------------------------------
self.xadc = XADC()
if toolchain == "vivado":
self.xadc = XADC()
# DNA --------------------------------------------------------------------------------------
self.dna = DNA()
self.dna.add_timing_constraints(platform, sys_clk_freq, self.crg.cd_sys.clk)
if toolchain == "vivado":
self.dna = DNA()
self.dna.add_timing_constraints(platform, sys_clk_freq, self.crg.cd_sys.clk)
# DDR3 SDRAM -------------------------------------------------------------------------------
if not self.integrated_main_ram_size: