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litex-boards
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targets: remove sdcard specific clock domain (now generated by the PHY).

This commit is contained in:
Florent Kermarrec 2020-07-03 20:09:30 +02:00
parent 31e6997e70
commit 7b1bf9d74a
5 changed files with 3 additions and 15 deletions
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2
litex_boards/targets/arty.py
View File

@ -31,7 +31,6 @@ class _CRG(Module):
self.clock_domains.cd_sys4x_dqs = ClockDomain(reset_less=True)
self.clock_domains.cd_clk200 = ClockDomain()
self.clock_domains.cd_eth = ClockDomain()
self.clock_domains.cd_sd = ClockDomain()
# # #
@ -43,7 +42,6 @@ class _CRG(Module):
pll.create_clkout(self.cd_sys4x_dqs, 4*sys_clk_freq, phase=90)
pll.create_clkout(self.cd_clk200, 200e6)
pll.create_clkout(self.cd_eth, 25e6)
pll.create_clkout(self.cd_sd, 10e6)
self.submodules.idelayctrl = S7IDELAYCTRL(self.cd_clk200)

4
litex_boards/targets/logicbone.py
View File

@ -33,8 +33,6 @@ class _CRG(Module):
self.clock_domains.cd_sys = ClockDomain()
self.clock_domains.cd_sys2x = ClockDomain()
self.clock_domains.cd_sys2x_i = ClockDomain(reset_less=True)
self.clock_domains.cd_sd = ClockDomain()
# # #
@ -57,7 +55,6 @@ class _CRG(Module):
pll.register_clkin(clk25, 25e6)
pll.create_clkout(self.cd_sys2x_i, 2*sys_clk_freq)
pll.create_clkout(self.cd_init, 24e6)
pll.create_clkout(self.cd_sd, 10e6)
self.specials += [
Instance("ECLKBRIDGECS",
i_CLK0 = self.cd_sys2x_i.clk,
@ -74,7 +71,6 @@ class _CRG(Module):
i_RST = self.reset,
o_CDIVX = self.cd_sys.clk),
AsyncResetSynchronizer(self.cd_init, ~por_done | ~pll.locked),
AsyncResetSynchronizer(self.cd_sd , ~por_done | ~pll.locked),
AsyncResetSynchronizer(self.cd_sys, ~por_done | ~pll.locked | self.reset),
AsyncResetSynchronizer(self.cd_sys2x, ~por_done | ~pll.locked | self.reset),
]

2
litex_boards/targets/nexys4ddr.py
View File

@ -30,7 +30,6 @@ class _CRG(Module):
self.clock_domains.cd_sys2x_dqs = ClockDomain(reset_less=True)
self.clock_domains.cd_clk200 = ClockDomain()
self.clock_domains.cd_eth = ClockDomain()
self.clock_domains.cd_sd = ClockDomain()
# # #
@ -42,7 +41,6 @@ class _CRG(Module):
pll.create_clkout(self.cd_sys2x_dqs, 2*sys_clk_freq, phase=90)
pll.create_clkout(self.cd_clk200, 200e6)
pll.create_clkout(self.cd_eth, 50e6)
pll.create_clkout(self.cd_sd, 10e6)
self.submodules.idelayctrl = S7IDELAYCTRL(self.cd_clk200)

5
litex_boards/targets/trellisboard.py
View File

@ -33,7 +33,6 @@ class _CRG(Module):
self.clock_domains.cd_sys = ClockDomain()
self.clock_domains.cd_sys2x = ClockDomain()
self.clock_domains.cd_sys2x_i = ClockDomain(reset_less=True)
self.clock_domains.cd_sd = ClockDomain()
# # #
@ -57,7 +56,6 @@ class _CRG(Module):
pll.register_clkin(clk12, 12e6)
pll.create_clkout(self.cd_sys2x_i, 2*sys_clk_freq)
pll.create_clkout(self.cd_init, 25e6)
pll.create_clkout(self.cd_sd, 16e6)
self.specials += [
Instance("ECLKBRIDGECS",
i_CLK0 = self.cd_sys2x_i.clk,
@ -75,7 +73,6 @@ class _CRG(Module):
i_RST = self.reset,
o_CDIVX = self.cd_sys.clk),
AsyncResetSynchronizer(self.cd_init, ~por_done | ~pll.locked | rst),
AsyncResetSynchronizer(self.cd_sd, ~por_done | ~pll.locked | rst),
AsyncResetSynchronizer(self.cd_sys, ~por_done | ~pll.locked | rst | self.reset),
AsyncResetSynchronizer(self.cd_sys2x, ~por_done | ~pll.locked | rst | self.reset),
]
@ -129,6 +126,8 @@ class BaseSoC(SoCCore):
sys_clk_freq = sys_clk_freq)
self.add_csr("leds")
self.add_ram("firmware_ram", 0x20000000, 0x10000)
# Build --------------------------------------------------------------------------------------------
def main():

5
litex_boards/targets/ulx3s.py
View File

@ -32,7 +32,6 @@ class _CRG(Module):
def __init__(self, platform, sys_clk_freq, with_usb_pll=False):
self.clock_domains.cd_sys = ClockDomain()
self.clock_domains.cd_sys_ps = ClockDomain(reset_less=True)
self.clock_domains.cd_sd = ClockDomain()
# # #
@ -46,9 +45,7 @@ class _CRG(Module):
pll.register_clkin(clk25, 25e6)
pll.create_clkout(self.cd_sys, sys_clk_freq)
pll.create_clkout(self.cd_sys_ps, sys_clk_freq, phase=90)
pll.create_clkout(self.cd_sd, 10e6)
self.specials += AsyncResetSynchronizer(self.cd_sys, ~pll.locked | rst)
self.specials += AsyncResetSynchronizer(self.cd_sd, ~pll.locked | rst)
self.specials += AsyncResetSynchronizer(self.cd_sys, ~pll.locked | rst)
# USB PLL
if with_usb_pll: