mirror of
https://github.com/litex-hub/litex-boards.git
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targets/litex_acorn_baseboard_mini: Make it similar to other targets and keep SoC + UART + DRAM + Ethernet.
This commit is contained in:
Florent Kermarrec
parent
aa34acc426
commit
7bc03e5fbc
1 changed files with 118 additions and 85 deletions
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@ -6,13 +6,12 @@
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# Copyright (c) 2021-2024 Florent Kermarrec <florent@enjoy-digital.fr>
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# SPDX-License-Identifier: BSD-2-Clause
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# Build/Use ----------------------------------------------------------------------------------------
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import os
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from migen import *
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from litex.gen import LiteXModule
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from litex.gen import *
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from litex.build.io import DifferentialInput
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from litex.build.openocd import OpenOCD
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from litex_boards.platforms import sqrl_acorn
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@ -23,44 +22,89 @@ from litex.soc.integration.builder import *
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from litex.soc.cores.clock import *
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from litex.soc.cores.led import LedChaser
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from litex.build.generic_platform import Subsignal, Pins
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from litex.build.generic_platform import IOStandard, Subsignal, Pins
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from litedram.modules import MT41K512M16
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from litedram.phy import s7ddrphy
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from liteeth.phy.a7_gtp import QPLLSettings, QPLL
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from liteeth.phy.a7_1000basex import A7_1000BASEX
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# Platform -----------------------------------------------------------------------------------------
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class Platform(sqrl_acorn.Platform):
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def create_programmer(self, name="openocd"):
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return OpenOCD("openocd_xc7_ft2232.cfg", "bscan_spi_xc7a200t.bit")
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_serial_io = [
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("serial", 0,
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Subsignal("tx", Pins("G1"), IOStandard("LVCMOS33")), # CLK_REQ
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Subsignal("rx", Pins("Y13"), IOStandard("LVCMOS18")), # SMB_ALERT_N
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),
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]
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# CRG ----------------------------------------------------------------------------------------------
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class CRG(Module):
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class CRG(LiteXModule):
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def __init__(self, platform, sys_clk_freq):
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self.rst = Signal()
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self.clock_domains.cd_sys = ClockDomain()
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self.clock_domains.cd_idelay = ClockDomain()
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self.cd_sys = ClockDomain()
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self.cd_sys4x = ClockDomain()
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self.cd_sys4x_dqs = ClockDomain()
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self.cd_idelay = ClockDomain()
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# Clk/Rst
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# Clk/Rst.
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clk200 = platform.request("clk200")
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clk200_se = Signal()
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self.specials += DifferentialInput(clk200.p, clk200.n, clk200_se)
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# PLL
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self.submodules.pll = pll = S7PLL()
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# PLL.
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self.pll = pll = S7PLL()
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self.comb += pll.reset.eq(self.rst)
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pll.register_clkin(clk200, 200e6)
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pll.create_clkout(self.cd_sys, sys_clk_freq, margin=0)
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# Ignore sys_clk to pll.clkin path created by SoC's rst.
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platform.add_false_path_constraints(self.cd_sys.clk, pll.clkin)
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pll.register_clkin(clk200_se, 200e6)
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pll.create_clkout(self.cd_sys, sys_clk_freq)
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pll.create_clkout(self.cd_sys4x, 4*sys_clk_freq)
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pll.create_clkout(self.cd_sys4x_dqs, 4*sys_clk_freq, phase=90)
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platform.add_false_path_constraints(self.cd_sys.clk, pll.clkin) # Ignore sys_clk to pll.clkin path created by SoC's rst.
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# IDelayCtrl.
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self.comb += self.cd_idelay.clk.eq(clk200_se)
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self.idelayctrl = S7IDELAYCTRL(self.cd_idelay)
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# BaseSoC -----------------------------------------------------------------------------------------
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class BaseSoC(SoCMini):
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def __init__(self, variant="cle-215+", sys_clk_freq=156.25e6, with_led_chaser=True, **kwargs):
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platform = sqrl_acorn.Platform(variant=variant)
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assert sys_clk_freq == 156.25e6
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# SoCCore ----------------------------------------------------------------------------------
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SoCMini.__init__(self, platform, sys_clk_freq, ident="LiteX SoC on Acorn CLE-101/215(+)")
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class BaseSoC(SoCCore):
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def __init__(self, variant="cle-215+", sys_clk_freq=156.25e6,
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with_ethernet = False,
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with_etherbone = False,
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eth_ip = "192.168.1.50",
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remote_ip = None,
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eth_dynamic_ip = False,
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with_led_chaser = True,
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**kwargs):
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platform = Platform(variant=variant)
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platform.add_extension(_serial_io, prepend=True)
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# CRG --------------------------------------------------------------------------------------
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self.submodules.crg = CRG(platform, sys_clk_freq)
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self.crg = CRG(platform, sys_clk_freq)
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# Etherbone --------------------------------------------------------------------------------
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# SoCCore ----------------------------------------------------------------------------------
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SoCCore.__init__(self, platform, sys_clk_freq, ident="LiteX SoC on Acorn CLE-101/215(+)", **kwargs)
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# DDR3 SDRAM -------------------------------------------------------------------------------
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if not self.integrated_main_ram_size:
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self.ddrphy = s7ddrphy.A7DDRPHY(platform.request("ddram"),
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memtype = "DDR3",
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nphases = 4,
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sys_clk_freq = sys_clk_freq)
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self.add_sdram("sdram",
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phy = self.ddrphy,
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module = MT41K512M16(sys_clk_freq, "1:4"),
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l2_cache_size = kwargs.get("l2_size", 8192)
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)
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# Ethernet / Etherbone ---------------------------------------------------------------------
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if with_ethernet or with_etherbone:
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_eth_io = [
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("sfp", 0,
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Subsignal("txp", Pins("D5")),
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@ -68,16 +112,9 @@ class BaseSoC(SoCMini):
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Subsignal("rxp", Pins("D11")),
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Subsignal("rxn", Pins("C11")),
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),
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("sfp", 1,
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Subsignal("txp", Pins("B4")),
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Subsignal("txn", Pins("A4")),
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Subsignal("rxp", Pins("B8")),
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Subsignal("rxn", Pins("A8")),
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),
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]
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platform.add_extension(_eth_io)
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# phy
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qpll_settings = QPLLSettings(
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refclksel = 0b001,
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fbdiv = 4,
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@ -88,39 +125,23 @@ class BaseSoC(SoCMini):
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print(qpll)
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self.submodules += qpll
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self.ethphy0 = A7_1000BASEX(
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self.ethphy = A7_1000BASEX(
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qpll_channel = qpll.channels[0],
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data_pads = self.platform.request("sfp", 0),
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data_pads = self.platform.request("sfp"),
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sys_clk_freq = self.clk_freq,
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rx_polarity = 1, # Inverted on Acorn
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rx_polarity = 1, # Inverted on Acorn.
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tx_polarity = 0 # Inverted on Acorn and on baseboard.
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)
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platform.add_platform_command("set_property SEVERITY {{Warning}} [get_drc_checks REQP-49]")
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self.add_etherbone(name="etherbone0",
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phy = self.ethphy0,
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phy_cd = "ethphy0_eth",
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mac_address = 0x10e2d5000000,
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ip_address = "192.168.1.50"
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)
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self.ethphy1 = A7_1000BASEX(
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qpll_channel = qpll.channels[0],
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data_pads = self.platform.request("sfp", 1),
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sys_clk_freq = self.clk_freq,
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rx_polarity = 1, # Inverted on Acorn
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tx_polarity = 0 # Inverted on Acorn and on baseboard.
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)
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platform.add_platform_command("set_property SEVERITY {{Warning}} [get_drc_checks REQP-49]")
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self.add_etherbone(name="etherbone1",
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phy = self.ethphy1,
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phy_cd = "ethphy1_eth",
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mac_address = 0x10e2d5000001,
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ip_address = "192.168.1.51"
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)
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if with_etherbone:
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self.add_etherbone(phy=self.ethphy, ip_address=eth_ip, with_ethmac=with_ethernet)
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elif with_ethernet:
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self.add_ethernet(phy=self.ethphy, dynamic_ip=eth_dynamic_ip, local_ip=eth_ip, remote_ip=remote_ip)
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# Leds -------------------------------------------------------------------------------------
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if with_led_chaser:
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self.submodules.leds = LedChaser(
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self.leds = LedChaser(
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pads = platform.request_all("user_led"),
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sys_clk_freq = sys_clk_freq)
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@ -131,10 +152,22 @@ def main():
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parser = LiteXArgumentParser(platform=sqrl_acorn.Platform, description="LiteX SoC on Acorn CLE-101/215(+).")
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parser.add_target_argument("--flash", action="store_true", help="Flash bitstream.")
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parser.add_target_argument("--variant", default="cle-215+", help="Board variant (cle-215+, cle-215 or cle-101).")
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parser.add_target_argument("--sys-clk-freq", default=156.25e6, type=float, help="System clock frequency.")
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parser.add_target_argument("--with-ethernet", action="store_true", help="Enable Ethernet support.")
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parser.add_target_argument("--with-etherbone", action="store_true", help="Enable Etherbone support.")
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parser.add_target_argument("--eth-ip", default="192.168.1.50", help="Ethernet/Etherbone IP address.")
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parser.add_target_argument("--remote-ip", default="192.168.1.100", help="Remote IP address of TFTP server.")
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parser.add_target_argument("--eth-dynamic-ip", action="store_true", help="Enable dynamic Ethernet IP addresses setting.")
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args = parser.parse_args()
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soc = BaseSoC(
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variant = args.variant,
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sys_clk_freq = args.sys_clk_freq,
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with_ethernet = args.with_ethernet,
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with_etherbone = args.with_etherbone,
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eth_ip = args.eth_ip,
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remote_ip = args.remote_ip,
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eth_dynamic_ip = args.eth_dynamic_ip,
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**parser.soc_argdict
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)
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