Add runber support
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db91eda899
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@ -19,6 +19,7 @@ vendors = [
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"lambdaconcept",
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"lambdaconcept",
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"linsn",
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"linsn",
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"muselab",
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"muselab",
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"myminieye",
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"numato",
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"numato",
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"qmtech",
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"qmtech",
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"qwertyembedded",
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"qwertyembedded",
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@ -0,0 +1,115 @@
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#
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# This file is part of LiteX-Boards.
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#
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# Copyright (c) 2021 Gwenhael Goavec-Merou <gwenhael.goavec-merou@trabucayre.com>
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# SPDX-License-Identifier: BSD-2-Clause
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from migen import *
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from litex.build.generic_platform import *
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from litex.build.gowin.platform import GowinPlatform
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from litex.build.openfpgaloader import OpenFPGALoader
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# IOs ----------------------------------------------------------------------------------------------
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_io = [
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# Clk / Rst
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("clk12", 0, Pins("4"), IOStandard("LVCMOS33")),
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# Leds
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("user_led", 0, Pins("23"), IOStandard("LVCMOS33")),
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("user_led", 1, Pins("24"), IOStandard("LVCMOS33")),
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("user_led", 2, Pins("25"), IOStandard("LVCMOS33")),
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("user_led", 3, Pins("26"), IOStandard("LVCMOS33")),
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("user_led", 4, Pins("27"), IOStandard("LVCMOS33")),
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("user_led", 5, Pins("28"), IOStandard("LVCMOS33")),
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("user_led", 6, Pins("29"), IOStandard("LVCMOS33")),
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("user_led", 7, Pins("30"), IOStandard("LVCMOS33")),
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# RGB led, active-low
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("rgb_led", 0,
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Subsignal("r", Pins("112")),
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Subsignal("g", Pins("114")),
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Subsignal("b", Pins("113")),
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IOStandard("LVCMOS33"),
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),
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("rgb_led", 1,
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Subsignal("r", Pins("106")),
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Subsignal("g", Pins("111")),
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Subsignal("b", Pins("110")),
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IOStandard("LVCMOS33"),
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),
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("rgb_led", 2,
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Subsignal("r", Pins("101")),
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Subsignal("g", Pins("104")),
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Subsignal("b", Pins("102")),
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IOStandard("LVCMOS33"),
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),
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("rgb_led", 3,
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Subsignal("r", Pins("98")),
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Subsignal("g", Pins("100")),
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Subsignal("b", Pins("99")),
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IOStandard("LVCMOS33"),
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),
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# Switches
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("user_sw", 0, Pins("75"), IOStandard("LVCMOS33")),
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("user_sw", 1, Pins("76"), IOStandard("LVCMOS33")),
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("user_sw", 2, Pins("78"), IOStandard("LVCMOS33")),
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("user_sw", 3, Pins("79"), IOStandard("LVCMOS33")),
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("user_sw", 4, Pins("80"), IOStandard("LVCMOS33")),
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("user_sw", 5, Pins("81"), IOStandard("LVCMOS33")),
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("user_sw", 6, Pins("82"), IOStandard("LVCMOS33")),
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("user_sw", 7, Pins("83"), IOStandard("LVCMOS33")),
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# Buttons.
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("user_btn", 0, Pins("58"), IOStandard("LVCMOS33")),
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("user_btn", 1, Pins("59"), IOStandard("LVCMOS33")),
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("user_btn", 2, Pins("60"), IOStandard("LVCMOS33")),
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("user_btn", 3, Pins("61"), IOStandard("LVCMOS33")),
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("user_btn", 4, Pins("62"), IOStandard("LVCMOS33")),
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("user_btn", 5, Pins("63"), IOStandard("LVCMOS33")),
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("user_btn", 6, Pins("64"), IOStandard("LVCMOS33")),
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("user_btn", 7, Pins("65"), IOStandard("LVCMOS33")),
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# Serial.
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# FT232H has only one interface -> use (arbitrary) two pins from J2 to
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# connect an external USB<->serial adapter
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("serial", 0,
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Subsignal("tx", Pins("116")), # J2.17
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Subsignal("rx", Pins("115")), # J2.18
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IOStandard("LVCMOS33")
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),
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# Seven Segment
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("seven_seg_dig", 0, Pins("137"), IOStandard("LVCMOS33")),
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("seven_seg_dig", 1, Pins("140"), IOStandard("LVCMOS33")),
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("seven_seg_dig", 2, Pins("141"), IOStandard("LVCMOS33")),
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("seven_seg_dig", 3, Pins("7"), IOStandard("LVCMOS33")),
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("seven_seg", 0, Pins("138 142 9 11 12 139 8 10"), IOStandard("LVCMOS33")),
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]
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# Connectors ---------------------------------------------------------------------------------------
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_connectors = [
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["J1", "- 38 39 40 41 42 43 44 66 67 68 69 70 71 72 96 95 94 93 -"],
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["J2", "- 136 135 134 133 132 131 130 129 128 123 122 121 120 119 118 117 116 115 -"],
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]
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# Platform -----------------------------------------------------------------------------------------
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class Platform(GowinPlatform):
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default_clk_name = "clk12"
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default_clk_period = 1e9/12e6
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def __init__(self):
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GowinPlatform.__init__(self, "GW1N-UV4LQ144C6/I5", _io, _connectors, toolchain="gowin", devicename="GW1N-4")
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self.toolchain.options["use_mspi_as_gpio"] = 1
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def create_programmer(self):
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return OpenFPGALoader("runber")
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def do_finalize(self, fragment):
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GowinPlatform.do_finalize(self, fragment)
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self.add_period_constraint(self.lookup_request("clk12", loose=True), 1e9/12e6)
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@ -0,0 +1,89 @@
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#!/usr/bin/env python3
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#
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# This file is part of LiteX-Boards.
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#
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# Copyright (c) 2021 Gwenhael Goavec-Merou <gwenhael.goavec-merou@trabucayre.com>
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# SPDX-License-Identifier: BSD-2-Clause
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import os
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import argparse
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from migen import *
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from migen.genlib.resetsync import AsyncResetSynchronizer
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from litex.soc.integration.soc_core import *
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from litex.soc.integration.builder import *
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from litex.soc.cores.led import LedChaser
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from litex_boards.platforms import runber
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# CRG ----------------------------------------------------------------------------------------------
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class _CRG(Module):
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def __init__(self, platform, sys_clk_freq):
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self.rst = Signal()
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self.clock_domains.cd_sys = ClockDomain()
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# # #
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# Clk / Rst
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clk12 = platform.request("clk12")
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rst_n = platform.request("user_btn", 0)
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self.comb += self.cd_sys.clk.eq(clk12)
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self.specials += AsyncResetSynchronizer(self.cd_sys, ~rst_n)
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# BaseSoC ------------------------------------------------------------------------------------------
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class BaseSoC(SoCCore):
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def __init__(self, sys_clk_freq=int(12e6), with_led_chaser=True, **kwargs):
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platform = runber.Platform()
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# Disable CPU for now.
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kwargs["cpu_type"] = None
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# SoCCore ----------------------------------------------------------------------------------
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SoCCore.__init__(self, platform, sys_clk_freq,
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ident = "LiteX SoC on Runber",
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ident_version = True,
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**kwargs)
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# CRG --------------------------------------------------------------------------------------
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self.submodules.crg = _CRG(platform, sys_clk_freq)
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# Leds -------------------------------------------------------------------------------------
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if with_led_chaser:
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self.submodules.leds = LedChaser(
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pads = platform.request_all("user_led"),
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sys_clk_freq = sys_clk_freq)
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# Build --------------------------------------------------------------------------------------------
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def main():
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parser = argparse.ArgumentParser(description="LiteX SoC on Runber")
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parser.add_argument("--build", action="store_true", help="Build bitstream")
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parser.add_argument("--load", action="store_true", help="Load bitstream")
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parser.add_argument("--flash", action="store_true", help="Flash Bitstream")
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parser.add_argument("--sys-clk-freq",default=12e6, help="System clock frequency (default: 12MHz)")
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builder_args(parser)
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soc_core_args(parser)
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args = parser.parse_args()
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soc = BaseSoC(
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sys_clk_freq = int(float(args.sys_clk_freq)),
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**soc_core_argdict(args)
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)
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builder = Builder(soc, **builder_argdict(args))
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builder.build(run=args.build)
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if args.load:
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prog = soc.platform.create_programmer()
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prog.load_bitstream(os.path.join(builder.gateware_dir, "impl", "pnr", "project.fs"))
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if args.flash:
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prog = soc.platform.create_programmer()
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prog.flash(0, os.path.join(builder.gateware_dir, "impl", "pnr", "project.fs"))
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if __name__ == "__main__":
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main()
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