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arty: Switch SPI Flash rate to 1:2 (DDR) (Possible on Arty since SPI Flash's clk does not require use of STARTUPE2).

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On the Digilent Arty, the SPI Flash's clk is connected to CCLK (that can be driven
through the STARTUPE2) but also to another generic IO that can be use to drive the
clock through DDR primitives.
This commit is contained in:
Florent Kermarrec 2021-09-07 15:04:38 +02:00
parent aa2209729f
commit 7fa22a494b
1 changed files with 1 additions and 1 deletions
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2
litex_boards/targets/digilent_arty.py
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@ -103,7 +103,7 @@ class BaseSoC(SoCCore):
if with_spi_flash:
from litespi.modules import S25FL128L
from litespi.opcodes import SpiNorFlashOpCodes as Codes
self.add_spi_flash(mode="4x", module=S25FL128L(Codes.READ_1_1_4), with_master=True)
self.add_spi_flash(mode="4x", module=S25FL128L(Codes.READ_1_1_4), rate="1:2", with_master=True)
# Leds -------------------------------------------------------------------------------------
if with_led_chaser: