test/test_targets: make sure all platforms are tested.
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@ -31,20 +31,26 @@ class TestTargets(unittest.TestCase):
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platforms = []
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# Xilinx Spartan6
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platforms.append("linsn_rv901t")
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platforms.append("minispartan6")
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platforms.append("pipistrello")
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platforms.append("sp605")
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# Xilinx Artix7
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platforms.append("ac701")
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platforms.append("aller")
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platforms.append("arty")
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platforms.append("mimas_a7")
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platforms.append("netv2")
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platforms.append("nexys4ddr")
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platforms.append("nexys_video")
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platforms.append("netv2")
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platforms.append("ac701")
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platforms.append("tagus")
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# Xilinx Kintex7
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platforms.append("kc705")
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platforms.append("genesys2")
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platforms.append("kc705")
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platforms.append("kx2")
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platforms.append("nereid")
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# Xilinx Kintex Ultrascale
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platforms.append("kcu105")
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@ -55,15 +61,16 @@ class TestTargets(unittest.TestCase):
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# Intel Cyclone5
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platforms.append("de1soc")
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platforms.append("de10nano")
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# Intel Max10
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platforms.append("de10lite")
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# Lattice iCE40
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platforms.append("tinyfpga_bx")
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platforms.append("fomu_evt")
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platforms.append("fomu_hacker")
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platforms.append("fomu_pvt")
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platforms.append("tinyfpga_bx")
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# Lattice MachXO2
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platforms.append("machxo3")
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@ -72,10 +79,12 @@ class TestTargets(unittest.TestCase):
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platforms.append("versa_ecp3")
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# Lattice ECP5
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platforms.append("versa_ecp5")
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platforms.append("ulx3s")
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platforms.append("trellisboard")
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platforms.append("ecp5_evn")
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platforms.append("hadbadge")
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platforms.append("orangecrab")
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platforms.append("trellisboard")
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platforms.append("ulx3s")
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platforms.append("versa_ecp5")
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# Microsemi PolarFire
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platforms.append("avalanche")
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