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platforms/vcu118: add missing Internal Vref configuration on DDR4 C1/C2 banks

This commit is contained in:
Florent Kermarrec 2020-02-25 18:32:42 +01:00
parent 4a84e9b08a
commit 83d2c71099
1 changed files with 8 additions and 0 deletions
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8
litex_boards/platforms/vcu118.py
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@ -165,3 +165,11 @@ class Platform(XilinxPlatform):
def do_finalize(self, fragment):
XilinxPlatform.do_finalize(self, fragment)
# DDR4 memory channel C1 Internal Vref
self.add_platform_command("set_property INTERNAL_VREF {{0.84}} [get_iobanks 71]")
self.add_platform_command("set_property INTERNAL_VREF {{0.84}} [get_iobanks 72]")
self.add_platform_command("set_property INTERNAL_VREF {{0.84}} [get_iobanks 73]")
# DDR4 memory channel C2 Internal Vref
self.add_platform_command("set_property INTERNAL_VREF {{0.84}} [get_iobanks 40]")
self.add_platform_command("set_property INTERNAL_VREF {{0.84}} [get_iobanks 41]")
self.add_platform_command("set_property INTERNAL_VREF {{0.84}} [get_iobanks 42]")