platforms/acorn_cle_215: integrated sdcard ios as extension.
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@ -33,16 +33,6 @@ _io = [
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IOStandard("LVCMOS33")
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IOStandard("LVCMOS33")
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),
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),
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# spisdcard (requires adapter off P2)
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("spisdcard", 0,
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Subsignal("clk", Pins("J2")),
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Subsignal("mosi", Pins("J5"), Misc("PULLUP True")),
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Subsignal("cs_n", Pins("H5"), Misc("PULLUP True")),
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Subsignal("miso", Pins("K2"), Misc("PULLUP True")),
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Misc("SLEW=FAST"),
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IOStandard("LVCMOS33"),
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),
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# pcie
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# pcie
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("pcie_clkreq_n", 0, Pins("G1"), IOStandard("LVCMOS33")),
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("pcie_clkreq_n", 0, Pins("G1"), IOStandard("LVCMOS33")),
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("pcie_x4", 0,
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("pcie_x4", 0,
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@ -83,6 +73,19 @@ _io = [
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),
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),
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]
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]
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_sdcard_io = [
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# SPI SDCard adapter on P2
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# https://spoolqueue.com/new-design/fpga/migen/litex/2020/08/11/acorn-cle-215.html
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("spisdcard", 0,
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Subsignal("clk", Pins("J2")),
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Subsignal("mosi", Pins("J5"), Misc("PULLUP True")),
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Subsignal("cs_n", Pins("H5"), Misc("PULLUP True")),
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Subsignal("miso", Pins("K2"), Misc("PULLUP True")),
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Misc("SLEW=FAST"),
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IOStandard("LVCMOS33"),
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),
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]
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# Platform -----------------------------------------------------------------------------------------
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# Platform -----------------------------------------------------------------------------------------
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class Platform(XilinxPlatform):
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class Platform(XilinxPlatform):
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@ -91,6 +94,7 @@ class Platform(XilinxPlatform):
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def __init__(self):
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def __init__(self):
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XilinxPlatform.__init__(self, "xc7a200t-fbg484-2", _io, toolchain="vivado")
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XilinxPlatform.__init__(self, "xc7a200t-fbg484-2", _io, toolchain="vivado")
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self.add_extension(_sdcard_io)
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self.add_platform_command("set_property INTERNAL_VREF 0.750 [get_iobanks 34]")
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self.add_platform_command("set_property INTERNAL_VREF 0.750 [get_iobanks 34]")
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self.toolchain.bitstream_commands = [
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self.toolchain.bitstream_commands = [
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