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re-compare and adjust to u250

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This commit is contained in:
Sergiu Mosanu 2021-01-26 23:03:09 -05:00
parent 5a1447dc5c
commit 84656a9c2e
2 changed files with 77 additions and 32 deletions
litex_boards
platforms
alveo_u280.py
targets
alveo_u280.py

73
litex_boards/platforms/alveo_u280.py
View file

@ -3,13 +3,15 @@
#
# Copyright (c) 2020 David Shah <dave@ds0.me>
# Copyright (c) 2020 Florent Kermarrec <florent@enjoy-digital.fr>
# Modified for Alveo U280 by Sergiu Mosanu based on XCU1525
# SPDX-License-Identifier: BSD-2-Clause
# Modified for Alveo U280 by Sergiu Mosanu based on XCU1525 and Alveo U250
from litex.build.generic_platform import Pins, Subsignal, IOStandard, Misc
from litex.build.xilinx import XilinxPlatform, VivadoProgrammer
# IOs ----------------------------------------------------------------------------------------------
# IOs -----------------------------------------------------------------------------------------------
_io = [
# Clk / Rst
@ -21,28 +23,56 @@ _io = [
Subsignal("n", Pins("BJ6"), IOStandard("LVDS")),
Subsignal("p", Pins("BH6"), IOStandard("LVDS")),
),
("cpu_reset", 0, Pins("L30"), IOStandard("LVCMOS18")),
# Leds
("gpio_led", 0, Pins("C32"), IOStandard("LVCMOS18")),
("gpio_led", 1, Pins("D32"), IOStandard("LVCMOS18")),
("gpio_led", 2, Pins("D31"), IOStandard("LVCMOS18")),
# Switches
("gpio_sw", 0, Pins("J30"), IOStandard("LVCMOS18")),
("gpio_sw", 1, Pins("J32"), IOStandard("LVCMOS18")),
("gpio_sw", 2, Pins("K32"), IOStandard("LVCMOS18")),
("gpio_sw", 3, Pins("K31"), IOStandard("LVCMOS18")),
# Serial
("serial", 0,
Subsignal("rx", Pins("A28"), IOStandard("LVCMOS18")),
Subsignal("tx", Pins("B33"), IOStandard("LVCMOS18")),
),
# DDR4 SDRAM
#("ddram_reset_gate", 0, Pins("AU21"), IOStandard("LVCMOS12")),
#("ddram_reset_gate", 0, Pins(""), IOStandard("LVCMOS12")),???
("ddram", 0,
Subsignal("a", Pins(
"BF46 BG43 BK45 BF42 BL45 BF43 BG42 BL43",
"BK43 BM42 BG45 BD41 BL42 BE44"), #"BE43 BL46 BH44"
"BK43 BM42 BG45 BD41 BL42 BE44"),
IOStandard("SSTL12_DCI")),
Subsignal("act_n", Pins("BH41"), IOStandard("SSTL12_DCI")),
Subsignal("ba", Pins("BH45 BM47"), IOStandard("SSTL12_DCI")),
Subsignal("bg", Pins("BF41 BE41"), IOStandard("SSTL12_DCI")),
Subsignal("ras_n", Pins("BH44"), IOStandard("SSTL12_DCI")), # A16
Subsignal("ba", Pins("BH45 BM47"), IOStandard("SSTL12_DCI")),
Subsignal("bg", Pins("BF41 BE41"), IOStandard("SSTL12_DCI")),
Subsignal("cas_n", Pins("BL46"), IOStandard("SSTL12_DCI")), # A15
Subsignal("we_n", Pins("BE43"), IOStandard("SSTL12_DCI")), # A14
Subsignal("cke", Pins("BH42"), IOStandard("SSTL12_DCI")),
Subsignal("cke", Pins("BH42"), IOStandard("SSTL12_DCI")),
Subsignal("clk_n", Pins("BJ46"), IOStandard("DIFF_SSTL12_DCI")),
Subsignal("clk_p", Pins("BH46"), IOStandard("DIFF_SSTL12_DCI")),
Subsignal("cs_n", Pins("BK46"), IOStandard("SSTL12_DCI")),
@ -56,28 +86,26 @@ _io = [
"BH50 BJ51 BH51 BH49 BK50 BK51 BJ49 BJ48",
"BN44 BN45 BM44 BM45 BP43 BP44 BN47 BP47"),
IOStandard("POD12_DCI"),
# Misc("OUTPUT_IMPEDANCE=RDRV_40_40"),
Misc("PRE_EMPHASIS=RDRV_240"),
Misc("EQUALIZATION=EQ_LEVEL2")),
Subsignal("dqs_n", Pins(
"BN30 BM29 BK30 BG30 BM35 BN35 BK35 BJ32",
"BM50 BP49 BF48 BG49 BJ47 BK49 BP46 BP42"), #"BJ54 BJ53"
IOStandard("DIFF_POD12"),
# Misc("OUTPUT_IMPEDANCE=RDRV_40_40"),
Misc("PRE_EMPHASIS=RDRV_240"),
Misc("EQUALIZATION=EQ_LEVEL2")),
Subsignal("dqs_p", Pins(
"BN29 BM28 BJ29 BG29 BL35 BM34 BK34 BH32",
"BM49 BP48 BF47 BG48 BH47 BK48 BN46 BN42"), #"BH54 BJ52"
IOStandard("DIFF_POD12"),
# Misc("OUTPUT_IMPEDANCE=RDRV_40_40"),
Misc("PRE_EMPHASIS=RDRV_240"),
Misc("EQUALIZATION=EQ_LEVEL2")),
Subsignal("odt", Pins("BG44"), IOStandard("SSTL12_DCI")),
Subsignal("ras_n", Pins("BH44"), IOStandard("SSTL12_DCI")), # A16
Subsignal("reset_n", Pins("BG33"), IOStandard("LVCMOS12")),
Subsignal("we_n", Pins("BE43"), IOStandard("SSTL12_DCI")), # A14
Misc("SLEW=FAST")
),
]
# Connectors ---------------------------------------------------------------------------------------
@ -100,10 +128,29 @@ class Platform(XilinxPlatform):
XilinxPlatform.do_finalize(self, fragment)
self.add_period_constraint(self.lookup_request("sysclk", 0, loose=True), 1e9/100e6)
self.add_period_constraint(self.lookup_request("sysclk", 1, loose=True), 1e9/100e6)
# For passively cooled boards, overheating is a significant risk if airflow isn't sufficient
self.add_platform_command("set_property BITSTREAM.CONFIG.OVERTEMPSHUTDOWN ENABLE [current_design]")
# Reduce programming time
self.add_platform_command("set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]")
# Other suggested configurations
self.add_platform_command("set_property CONFIG_VOLTAGE 1.8 [current_design]")
self.add_platform_command("set_property BITSTREAM.CONFIG.CONFIGFALLBACK Enable [current_design]")

36
litex_boards/targets/alveo_u280.py
View file

@ -3,12 +3,13 @@
#
# This file is part of LiteX-Boards.
#
# Copyright (c) 2020 Fei Gao <feig@princeton.edu>
# Copyright (c) 2020 Florent Kermarrec <florent@enjoy-digital.fr>
# Modified for Alveo U280 by Sergiu Mosanu based on XCU1525
# Copyright (c) 2020 David Shah <dave@ds0.me>
# Modified for Alveo U280 by Sergiu Mosanu based on XCU1525 and Alveo U250
# SPDX-License-Identifier: BSD-2-Clause
import os
import argparse
import argparse, os
from migen import *
from migen.genlib.resetsync import AsyncResetSynchronizer
@ -29,7 +30,7 @@ from litepcie.software import generate_litepcie_software
# CRG ----------------------------------------------------------------------------------------------
class _CRG(Module):
def __init__(self, platform, sys_clk_freq, ddram_channel):
def __init__(self, platform, sys_clk_freq):
self.rst = Signal()
self.clock_domains.cd_sys = ClockDomain()
self.clock_domains.cd_sys4x = ClockDomain(reset_less=True)
@ -40,8 +41,7 @@ class _CRG(Module):
self.submodules.pll = pll = USMMCM(speedgrade=-2)
self.comb += pll.reset.eq(self.rst)
#pll.register_clkin(platform.request("clk300", ddram_channel), 300e6)
pll.register_clkin(platform.request("sysclk", ddram_channel), 100e6)
pll.register_clkin(platform.request("sysclk", 0), 100e6)
pll.create_clkout(self.cd_pll4x, sys_clk_freq*4, buf=None, with_reset=False)
pll.create_clkout(self.cd_idelay, 500e6, with_reset=False)
platform.add_false_path_constraints(self.cd_sys.clk, pll.clkin) # Ignore sys_clk to pll.clkin path created by SoC's rst.
@ -60,22 +60,22 @@ class _CRG(Module):
# BaseSoC ------------------------------------------------------------------------------------------
class BaseSoC(SoCCore):
def __init__(self, sys_clk_freq=int(125e6), ddram_channel=0, with_pcie=False, **kwargs):
def __init__(self, sys_clk_freq=int(125e6), with_pcie=False, **kwargs):
platform = alveo_u280.Platform()
# SoCCore ----------------------------------------------------------------------------------
SoCCore.__init__(self, platform, sys_clk_freq,
ident = "LiteX SoC on Alveo U280",
ident_version = True,
# bus_standard = "axi-lite", #
**kwargs)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform, sys_clk_freq, ddram_channel)
self.submodules.crg = _CRG(platform, sys_clk_freq)
# DDR4 SDRAM -------------------------------------------------------------------------------
if not self.integrated_main_ram_size:
self.submodules.ddrphy = usddrphy.USPDDRPHY(
pads = platform.request("ddram", ddram_channel),
self.submodules.ddrphy = usddrphy.USPDDRPHY(platform.request("ddram"),
memtype = "DDR4",
sys_clk_freq = sys_clk_freq,
iodelay_clk_freq = 500e6,
@ -106,20 +106,18 @@ class BaseSoC(SoCCore):
def main():
parser = argparse.ArgumentParser(description="LiteX SoC on Alveo U280")
parser.add_argument("--build", action="store_true", help="Build bitstream")
parser.add_argument("--load", action="store_true", help="Load bitstream")
parser.add_argument("--sys-clk-freq", default=125e6, help="System clock frequency (default: 125MHz)")
parser.add_argument("--ddram-channel", default="0", help="DDRAM channel (default: 0)")
parser.add_argument("--with-pcie", action="store_true", help="Enable PCIe support")
parser.add_argument("--driver", action="store_true", help="Generate PCIe driver")
parser.add_argument("--build", action="store_true", help="Build bitstream")
parser.add_argument("--load", action="store_true", help="Load bitstream")
parser.add_argument("--sys-clk-freq", default=125e6, help="System clock frequency (default: 125MHz)")
parser.add_argument("--with-pcie", action="store_true", help="Enable PCIe support")
parser.add_argument("--driver", action="store_true", help="Generate PCIe driver")
builder_args(parser)
soc_sdram_args(parser)
args = parser.parse_args()
soc = BaseSoC(
sys_clk_freq = int(float(args.sys_clk_freq)),
ddram_channel = int(args.ddram_channel, 0),
with_pcie = args.with_pcie,
sys_clk_freq = int(float(args.sys_clk_freq)),
with_pcie = args.with_pcie,
**soc_sdram_argdict(args)
)
builder = Builder(soc, **builder_argdict(args))