de10nano/Mister: review/simplify.
This commit is contained in:
Florent Kermarrec
parent
64372d7876
commit
85cac7abc0
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@ -29,16 +29,15 @@ _io = [
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("user_sw", 2, Pins("W21"), IOStandard("3.3-V LVTTL")),
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("user_sw", 3, Pins("W20"), IOStandard("3.3-V LVTTL")),
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# uncomment appropriate serial for board
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("serial", 0,
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Subsignal("tx", Pins("AH9"), IOStandard("3.3-V LVTTL")), # user i/o port on mister i/o board
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Subsignal("rx", Pins("AG11"), IOStandard("3.3-V LVTTL")) # user i/o port on mister i/o board
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Subsignal("tx", Pins("AH9"), IOStandard("3.3-V LVTTL")), # User I/O port on Mister
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Subsignal("rx", Pins("AG11"), IOStandard("3.3-V LVTTL")) # User I/O port on Mister
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),
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# ("serial", 0,
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# Subsignal("tx", Pins("AF13"), IOStandard("3.3-V LVTTL")), # Arduino_IO1
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# Subsignal("rx", Pins("AG13"), IOStandard("3.3-V LVTTL")) # Arduino_IO0
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# ),
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("serial", 1,
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Subsignal("tx", Pins("AF13"), IOStandard("3.3-V LVTTL")), # Arduino_IO1
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Subsignal("rx", Pins("AG13"), IOStandard("3.3-V LVTTL")) # Arduino_IO0
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),
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("g_sensor", 0,
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Subsignal("int", Pins("A17")),
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@ -55,7 +54,6 @@ _io = [
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IOStandard("3.3-V LVTTL")
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),
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# HDMI consists of HDMI + I2C for control + I2S for audio
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("hdmi", 0,
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Subsignal("tx_d_r", Pins("AS12 AE12 W8 Y8 AD11 AD10 AE11 Y5")),
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Subsignal("tx_d_g", Pins("AF10 Y4 AE9 AB4 AE7 AF6 AF8 AF5")),
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@ -14,56 +14,17 @@ from litex.build.io import DDROutput
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from litex_boards.platforms import de10nano
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from litex.soc.cores.clock import CycloneVPLL
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from litex.soc.integration.soc import SoCRegion
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from litex.soc.integration.soc_core import *
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from litex.soc.integration.soc_sdram import *
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from litex.soc.integration.builder import *
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# de10nano specific
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from litex.soc.cores.led import LedChaser
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# de10nano 128MB sdram
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from litedram.modules import SDRAMModule
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from litedram.modules import _TechnologyTimings
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from litedram.modules import _SpeedgradeTimings
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from litedram.modules import AS4C32M16
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from litedram.phy import GENSDRPHY
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# de10nano buses
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from litex.soc.interconnect.axi import *
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from litex.soc.interconnect import wishbone
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# VGA terminal
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from litevideo.terminal.core import Terminal
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# MiSTer I/O definitions
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# Light up the top user leds on the mister i/o board
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class MiSTerOutputs(Module):
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def __init__(self, pads):
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if hasattr(pads, 'led_power'):
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led_power_pin = Signal()
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self.comb += pads.led_power.eq(0)
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if hasattr(pads, 'led_user'):
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led_user_pin = Signal()
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self.comb += pads.led_user.eq(0)
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if hasattr(pads, 'led_hdd'):
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led_hdd_pin = Signal()
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self.comb += pads.led_hdd.eq(0)
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led_power_pin.eq(1)
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led_user_pin.eq(0)
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led_hdd_pin.eq(0)
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# MiSTer 128MB SDRAM
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class MiSTer128SDRAM(SDRAMModule): #4 x AS4C32M16 32MB=4*8192*512 (hopefully 128MB=4*32768*512 or 16*8192*512)
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memtype = "SDR"
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# geometry
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nbanks = 4
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nrows = 16384
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ncols = 1024
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# timings
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technology_timings = _TechnologyTimings(tREFI=64e6/8192, tWTR=(2, None), tCCD=(1, None), tRRD=None)
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speedgrade_timings = {"default": _SpeedgradeTimings(tRP=18, tRCD=18, tWR=12, tRFC=(None, 60), tFAW=None, tRAS=None)}
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# CRG ----------------------------------------------------------------------------------------------
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class _CRG(Module):
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@ -82,7 +43,7 @@ class _CRG(Module):
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pll.create_clkout(self.cd_sys, sys_clk_freq)
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pll.create_clkout(self.cd_sys_ps, sys_clk_freq, phase=90)
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pll.create_clkout(self.cd_vga, 25e6)
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# SDRAM clock
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if with_sdram:
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self.specials += DDROutput(1, 0, platform.request("sdram_clock"), ClockSignal("sys_ps"))
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@ -90,49 +51,21 @@ class _CRG(Module):
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# BaseSoC ------------------------------------------------------------------------------------------
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class BaseSoC(SoCCore):
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def __init__(self, sys_clk_freq=int(50e6), **kwargs):
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platform = de10nano.Platform()
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# SoCCore ---------------------------------------------------------------------------------
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SoCCore.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs)
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# CRG --------------------------------------------------------------------------------------
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self.submodules.crg = _CRG(platform, sys_clk_freq)
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# Leds -------------------------------------------------------------------------------------
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self.submodules.leds = LedChaser(
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pads = Cat(*[platform.request("user_led", i) for i in range(8)]),
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sys_clk_freq = sys_clk_freq)
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self.add_csr("leds")
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# MiSTerSDRAMSoC -----------------------------------------------------------------------------------
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class MiSTerSDRAMSoC(SoCCore):
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def __init__(self, sys_clk_freq=int(50e6), **kwargs):
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def __init__(self, sys_clk_freq=int(50e6), with_mister_sdram=False, with_mister_vga=False, **kwargs):
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platform = de10nano.Platform()
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# SoCCore ----------------------------------------------------------------------------------
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SoCCore.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs)
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# CRG --------------------------------------------------------------------------------------
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self.submodules.crg = _CRG(platform, sys_clk_freq, with_sdram=True)
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self.submodules.crg = _CRG(platform, sys_clk_freq, with_sdram=with_mister_sdram)
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# Leds -------------------------------------------------------------------------------------
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self.submodules.leds = LedChaser(
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pads = Cat(*[platform.request("user_led", i) for i in range(8)]),
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sys_clk_freq = sys_clk_freq)
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self.add_csr("leds")
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# mister user leds
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self.submodules.mister_outputs = mister_outputs = MiSTerOutputs(platform.request("mister_outputs",0))
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self.add_csr("mister_outputs")
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# SDR SDRAM --------------------------------------------------------------------------------
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if not self.integrated_main_ram_size:
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if with_mister_sdram and not self.integrated_main_ram_size:
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self.submodules.sdrphy = GENSDRPHY(platform.request("sdram"))
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self.add_sdram("sdram",
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phy = self.sdrphy,
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module = MiSTer128SDRAM(self.clk_freq, "1:1"),
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module = AS4C32M16(self.clk_freq, "1:1"),
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origin = self.mem_map["main_ram"],
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size = kwargs.get("max_sdram_size", 0x40000000),
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l2_cache_size = kwargs.get("l2_size", 8192),
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@ -140,27 +73,24 @@ class MiSTerSDRAMSoC(SoCCore):
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l2_cache_reverse = True
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)
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# VGA terminal
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self.mem_map["terminal"] = 0x30000000
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self.submodules.terminal = terminal = Terminal()
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self.add_wb_slave(self.mem_map["terminal"], self.terminal.bus, 8896)
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self.add_memory_region("terminal", self.mem_map["terminal"], 8896, type="cached+linker")
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# VGA terminal -----------------------------------------------------------------------------
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if with_mister_vga:
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self.submodules.terminal = terminal = Terminal()
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self.bus.add_slave("terminal", self.terminal.bus, region=SoCRegion(origin=0x30000000, size=0x10000))
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vga_pads = platform.request("vga")
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self.comb += [
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vga_pads.vsync.eq(terminal.vsync),
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vga_pads.hsync.eq(terminal.hsync),
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vga_pads.red.eq(terminal.red[2:8]),
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vga_pads.green.eq(terminal.green[2:8]),
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vga_pads.blue.eq(terminal.blue[2:8])
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]
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# Connect VGA pins
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vga = platform.request("vga", 0)
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self.comb += [
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vga.vsync.eq(terminal.vsync),
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vga.hsync.eq(terminal.hsync),
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vga.red.eq(terminal.red[2:8]),
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vga.green.eq(terminal.green[2:8]),
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vga.blue.eq(terminal.blue[2:8])
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]
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vga.en.eq(1)
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# self.add_csr("terminal")
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# AXI Bus
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# axibus = AXILiteInterface()
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# Leds -------------------------------------------------------------------------------------
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self.submodules.leds = LedChaser(
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pads = Cat(*[platform.request("user_led", i) for i in range(8)]),
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sys_clk_freq = sys_clk_freq)
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self.add_csr("leds")
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# Build --------------------------------------------------------------------------------------------
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@ -170,12 +100,13 @@ def main():
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parser.add_argument("--load", action="store_true", help="Load bitstream")
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builder_args(parser)
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soc_sdram_args(parser)
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parser.add_argument("--with-mister-sdram", action="store_true", help="Enable MiSTer SDRAM expansion board")
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parser.add_argument("--with-mister-sdram", action="store_true", help="Enable SDRAM with MiSTer expansion board")
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parser.add_argument("--with-mister-vga", action="store_true", help="Enable VGA with Mister expansion board")
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args = parser.parse_args()
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if args.with_mister_sdram:
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soc = MiSTerSDRAMSoC(**soc_sdram_argdict(args))
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else:
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soc = BaseSoC(**soc_sdram_argdict(args))
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soc = BaseSoC(
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with_mister_sdram = args.with_mister_sdram,
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with_mister_vga = args.with_mister_vga,
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**soc_sdram_argdict(args))
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builder = Builder(soc, **builder_argdict(args))
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builder.build(run=args.build)
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