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de10nano/Mister: review/simplify.

This commit is contained in:
Florent Kermarrec 2020-06-11 19:54:55 +02:00
parent 64372d7876
commit 85cac7abc0
2 changed files with 36 additions and 107 deletions
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14
litex_boards/platforms/de10nano.py
View File

@ -29,16 +29,15 @@ _io = [
("user_sw", 2, Pins("W21"), IOStandard("3.3-V LVTTL")), ("user_sw", 2, Pins("W21"), IOStandard("3.3-V LVTTL")),
("user_sw", 3, Pins("W20"), IOStandard("3.3-V LVTTL")), ("user_sw", 3, Pins("W20"), IOStandard("3.3-V LVTTL")),
# uncomment appropriate serial for board
("serial", 0, ("serial", 0,
Subsignal("tx", Pins("AH9"), IOStandard("3.3-V LVTTL")), # user i/o port on mister i/o board Subsignal("tx", Pins("AH9"), IOStandard("3.3-V LVTTL")), # User I/O port on Mister
Subsignal("rx", Pins("AG11"), IOStandard("3.3-V LVTTL")) # user i/o port on mister i/o board Subsignal("rx", Pins("AG11"), IOStandard("3.3-V LVTTL")) # User I/O port on Mister
), ),
# ("serial", 0, ("serial", 1,
# Subsignal("tx", Pins("AF13"), IOStandard("3.3-V LVTTL")), # Arduino_IO1 Subsignal("tx", Pins("AF13"), IOStandard("3.3-V LVTTL")), # Arduino_IO1
# Subsignal("rx", Pins("AG13"), IOStandard("3.3-V LVTTL")) # Arduino_IO0 Subsignal("rx", Pins("AG13"), IOStandard("3.3-V LVTTL")) # Arduino_IO0
# ), ),
("g_sensor", 0, ("g_sensor", 0,
Subsignal("int", Pins("A17")), Subsignal("int", Pins("A17")),
@ -55,7 +54,6 @@ _io = [
IOStandard("3.3-V LVTTL") IOStandard("3.3-V LVTTL")
), ),
# HDMI consists of HDMI + I2C for control + I2S for audio
("hdmi", 0, ("hdmi", 0,
Subsignal("tx_d_r", Pins("AS12 AE12 W8 Y8 AD11 AD10 AE11 Y5")), Subsignal("tx_d_r", Pins("AS12 AE12 W8 Y8 AD11 AD10 AE11 Y5")),
Subsignal("tx_d_g", Pins("AF10 Y4 AE9 AB4 AE7 AF6 AF8 AF5")), Subsignal("tx_d_g", Pins("AF10 Y4 AE9 AB4 AE7 AF6 AF8 AF5")),

121
litex_boards/targets/de10nano.py
View File

@ -14,56 +14,17 @@ from litex.build.io import DDROutput
from litex_boards.platforms import de10nano from litex_boards.platforms import de10nano
from litex.soc.cores.clock import CycloneVPLL from litex.soc.cores.clock import CycloneVPLL
from litex.soc.integration.soc import SoCRegion
from litex.soc.integration.soc_core import * from litex.soc.integration.soc_core import *
from litex.soc.integration.soc_sdram import * from litex.soc.integration.soc_sdram import *
from litex.soc.integration.builder import * from litex.soc.integration.builder import *
# de10nano specific
from litex.soc.cores.led import LedChaser from litex.soc.cores.led import LedChaser
# de10nano 128MB sdram from litedram.modules import AS4C32M16
from litedram.modules import SDRAMModule
from litedram.modules import _TechnologyTimings
from litedram.modules import _SpeedgradeTimings
from litedram.phy import GENSDRPHY from litedram.phy import GENSDRPHY
# de10nano buses
from litex.soc.interconnect.axi import *
from litex.soc.interconnect import wishbone
# VGA terminal
from litevideo.terminal.core import Terminal from litevideo.terminal.core import Terminal
# MiSTer I/O definitions
# Light up the top user leds on the mister i/o board
class MiSTerOutputs(Module):
def __init__(self, pads):
if hasattr(pads, 'led_power'):
led_power_pin = Signal()
self.comb += pads.led_power.eq(0)
if hasattr(pads, 'led_user'):
led_user_pin = Signal()
self.comb += pads.led_user.eq(0)
if hasattr(pads, 'led_hdd'):
led_hdd_pin = Signal()
self.comb += pads.led_hdd.eq(0)
led_power_pin.eq(1)
led_user_pin.eq(0)
led_hdd_pin.eq(0)
# MiSTer 128MB SDRAM
class MiSTer128SDRAM(SDRAMModule): #4 x AS4C32M16 32MB=4*8192*512 (hopefully 128MB=4*32768*512 or 16*8192*512)
memtype = "SDR"
# geometry
nbanks = 4
nrows = 16384
ncols = 1024
# timings
technology_timings = _TechnologyTimings(tREFI=64e6/8192, tWTR=(2, None), tCCD=(1, None), tRRD=None)
speedgrade_timings = {"default": _SpeedgradeTimings(tRP=18, tRCD=18, tWR=12, tRFC=(None, 60), tFAW=None, tRAS=None)}
# CRG ---------------------------------------------------------------------------------------------- # CRG ----------------------------------------------------------------------------------------------
class _CRG(Module): class _CRG(Module):
@ -90,49 +51,21 @@ class _CRG(Module):
# BaseSoC ------------------------------------------------------------------------------------------ # BaseSoC ------------------------------------------------------------------------------------------
class BaseSoC(SoCCore): class BaseSoC(SoCCore):
def __init__(self, sys_clk_freq=int(50e6), **kwargs): def __init__(self, sys_clk_freq=int(50e6), with_mister_sdram=False, with_mister_vga=False, **kwargs):
platform = de10nano.Platform()
# SoCCore ---------------------------------------------------------------------------------
SoCCore.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform, sys_clk_freq)
# Leds -------------------------------------------------------------------------------------
self.submodules.leds = LedChaser(
pads = Cat(*[platform.request("user_led", i) for i in range(8)]),
sys_clk_freq = sys_clk_freq)
self.add_csr("leds")
# MiSTerSDRAMSoC -----------------------------------------------------------------------------------
class MiSTerSDRAMSoC(SoCCore):
def __init__(self, sys_clk_freq=int(50e6), **kwargs):
platform = de10nano.Platform() platform = de10nano.Platform()
# SoCCore ---------------------------------------------------------------------------------- # SoCCore ----------------------------------------------------------------------------------
SoCCore.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs) SoCCore.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs)
# CRG -------------------------------------------------------------------------------------- # CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform, sys_clk_freq, with_sdram=True) self.submodules.crg = _CRG(platform, sys_clk_freq, with_sdram=with_mister_sdram)
# Leds -------------------------------------------------------------------------------------
self.submodules.leds = LedChaser(
pads = Cat(*[platform.request("user_led", i) for i in range(8)]),
sys_clk_freq = sys_clk_freq)
self.add_csr("leds")
# mister user leds
self.submodules.mister_outputs = mister_outputs = MiSTerOutputs(platform.request("mister_outputs",0))
self.add_csr("mister_outputs")
# SDR SDRAM -------------------------------------------------------------------------------- # SDR SDRAM --------------------------------------------------------------------------------
if not self.integrated_main_ram_size: if with_mister_sdram and not self.integrated_main_ram_size:
self.submodules.sdrphy = GENSDRPHY(platform.request("sdram")) self.submodules.sdrphy = GENSDRPHY(platform.request("sdram"))
self.add_sdram("sdram", self.add_sdram("sdram",
phy = self.sdrphy, phy = self.sdrphy,
module = MiSTer128SDRAM(self.clk_freq, "1:1"), module = AS4C32M16(self.clk_freq, "1:1"),
origin = self.mem_map["main_ram"], origin = self.mem_map["main_ram"],
size = kwargs.get("max_sdram_size", 0x40000000), size = kwargs.get("max_sdram_size", 0x40000000),
l2_cache_size = kwargs.get("l2_size", 8192), l2_cache_size = kwargs.get("l2_size", 8192),
@ -140,27 +73,24 @@ class MiSTerSDRAMSoC(SoCCore):
l2_cache_reverse = True l2_cache_reverse = True
) )
# VGA terminal # VGA terminal -----------------------------------------------------------------------------
self.mem_map["terminal"] = 0x30000000 if with_mister_vga:
self.submodules.terminal = terminal = Terminal() self.submodules.terminal = terminal = Terminal()
self.add_wb_slave(self.mem_map["terminal"], self.terminal.bus, 8896) self.bus.add_slave("terminal", self.terminal.bus, region=SoCRegion(origin=0x30000000, size=0x10000))
self.add_memory_region("terminal", self.mem_map["terminal"], 8896, type="cached+linker") vga_pads = platform.request("vga")
# Connect VGA pins
vga = platform.request("vga", 0)
self.comb += [ self.comb += [
vga.vsync.eq(terminal.vsync), vga_pads.vsync.eq(terminal.vsync),
vga.hsync.eq(terminal.hsync), vga_pads.hsync.eq(terminal.hsync),
vga.red.eq(terminal.red[2:8]), vga_pads.red.eq(terminal.red[2:8]),
vga.green.eq(terminal.green[2:8]), vga_pads.green.eq(terminal.green[2:8]),
vga.blue.eq(terminal.blue[2:8]) vga_pads.blue.eq(terminal.blue[2:8])
] ]
vga.en.eq(1)
# self.add_csr("terminal") # Leds -------------------------------------------------------------------------------------
self.submodules.leds = LedChaser(
# AXI Bus pads = Cat(*[platform.request("user_led", i) for i in range(8)]),
# axibus = AXILiteInterface() sys_clk_freq = sys_clk_freq)
self.add_csr("leds")
# Build -------------------------------------------------------------------------------------------- # Build --------------------------------------------------------------------------------------------
@ -170,12 +100,13 @@ def main():
parser.add_argument("--load", action="store_true", help="Load bitstream") parser.add_argument("--load", action="store_true", help="Load bitstream")
builder_args(parser) builder_args(parser)
soc_sdram_args(parser) soc_sdram_args(parser)
parser.add_argument("--with-mister-sdram", action="store_true", help="Enable MiSTer SDRAM expansion board") parser.add_argument("--with-mister-sdram", action="store_true", help="Enable SDRAM with MiSTer expansion board")
parser.add_argument("--with-mister-vga", action="store_true", help="Enable VGA with Mister expansion board")
args = parser.parse_args() args = parser.parse_args()
if args.with_mister_sdram: soc = BaseSoC(
soc = MiSTerSDRAMSoC(**soc_sdram_argdict(args)) with_mister_sdram = args.with_mister_sdram,
else: with_mister_vga = args.with_mister_vga,
soc = BaseSoC(**soc_sdram_argdict(args)) **soc_sdram_argdict(args))
builder = Builder(soc, **builder_argdict(args)) builder = Builder(soc, **builder_argdict(args))
builder.build(run=args.build) builder.build(run=args.build)