mirror of
https://github.com/litex-hub/litex-boards.git
synced 2025-01-03 03:43:36 -05:00
targets: update PCIe on Numato targets.
Should be compatible with software from: https://github.com/enjoy-digital/netv2.
This commit is contained in:
Florent Kermarrec
parent
6e6b6dac55
commit
85f38876c2
3 changed files with 194 additions and 112 deletions
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@ -9,14 +9,20 @@ import sys
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from migen import *
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from litex.build.generic_platform import *
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from litex.build import tools
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from litex_boards.platforms import aller
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from litex.soc.interconnect.csr import *
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from litex.soc.integration.soc_core import *
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from litex.soc.integration.soc_sdram import *
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from litex.soc.integration.builder import *
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from litex.soc.integration.export import *
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from litex.soc.cores.clock import *
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from litex.soc.cores import dna, xadc
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from litex.soc.cores.uart import *
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from litex.soc.integration.cpu_interface import get_csr_header
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from litex.soc.cores.dna import DNA
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from litex.soc.cores.xadc import XADC
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from litex.soc.cores.icap import ICAP
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from litedram.modules import MT41J128M16
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from litedram.phy import s7ddrphy
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@ -26,18 +32,21 @@ from litepcie.core import LitePCIeEndpoint, LitePCIeMSI
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from litepcie.frontend.dma import LitePCIeDMA
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from litepcie.frontend.wishbone import LitePCIeWishboneBridge
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from litex_boards.platforms import aller
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# CRG ----------------------------------------------------------------------------------------------
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class CRG(Module):
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class CRG(Module, AutoCSR):
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def __init__(self, platform, sys_clk_freq):
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self.reset = CSR() # FIXME: not used for now
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self.clock_domains.cd_sys = ClockDomain()
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self.clock_domains.cd_sys4x = ClockDomain(reset_less=True)
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self.clock_domains.cd_sys4x_dqs = ClockDomain(reset_less=True)
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self.clock_domains.cd_clk200 = ClockDomain()
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clk100 = platform.request("clk100")
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platform.add_period_constraint(clk100, 1e9/100e6)
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self.submodules.pll = pll = S7PLL()
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pll.register_clkin(clk100, 100e6)
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@ -51,15 +60,13 @@ class CRG(Module):
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# PCIeSoC -----------------------------------------------------------------------------------------
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class PCIeSoC(SoCCore):
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SoCCore.mem_map["csr"] = 0x80000000
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SoCCore.mem_map["rom"] = 0x20000000
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def __init__(self, platform, **kwargs):
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sys_clk_freq = int(100e6)
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# SoCCore ----------------------------------------------------------------------------------
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SoCCore.__init__(self, platform, sys_clk_freq,
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ident = "LiteX SoC on Tagus", ident_version=True,
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ident = "LiteX SoC on Aller",
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ident_version = True,
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**kwargs)
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# CRG --------------------------------------------------------------------------------------
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@ -67,13 +74,19 @@ class PCIeSoC(SoCCore):
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self.add_csr("crg")
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# DNA --------------------------------------------------------------------------------------
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self.submodules.dna = dna.DNA()
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self.submodules.dna = DNA()
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self.dna.add_timing_constraints(platform, sys_clk_freq, self.crg.cd_sys.clk)
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self.add_csr("dna")
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# XADC -------------------------------------------------------------------------------------
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self.submodules.xadc = xadc.XADC()
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self.submodules.xadc = XADC()
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self.add_csr("xadc")
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# ICAP -------------------------------------------------------------------------------------
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self.submodules.icap = ICAP(platform)
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self.icap.add_timing_constraints(platform, sys_clk_freq, self.crg.cd_sys.clk)
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self.add_csr("icap")
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# DDR3 SDRAM -------------------------------------------------------------------------------
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if not self.integrated_main_ram_size:
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self.submodules.ddrphy = s7ddrphy.A7DDRPHY(platform.request("ddram"),
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@ -93,59 +106,74 @@ class PCIeSoC(SoCCore):
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)
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# PCIe -------------------------------------------------------------------------------------
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# pcie phy
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self.submodules.pcie_phy = S7PCIEPHY(platform, platform.request("pcie_x1"), bar0_size=0x20000)
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# PHY
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self.submodules.pcie_phy = S7PCIEPHY(platform, platform.request("pcie_x1"),
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data_width = 64,
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bar0_size = 0x20000)
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platform.add_false_path_constraints(self.crg.cd_sys.clk, self.pcie_phy.cd_pcie.clk)
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self.add_csr("pcie_phy")
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# pcie endpoint
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# Endpoint
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self.submodules.pcie_endpoint = LitePCIeEndpoint(self.pcie_phy)
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# pcie wishbone bridge
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self.submodules.pcie_wishbone = LitePCIeWishboneBridge(self.pcie_endpoint,
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lambda a: 1, base_address=self.mem_map["csr"])
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self.add_wb_master(self.pcie_wishbone.wishbone)
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# Wishbone bridge
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self.submodules.pcie_bridge = LitePCIeWishboneBridge(self.pcie_endpoint,
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base_address = self.mem_map["csr"])
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self.add_wb_master(self.pcie_bridge.wishbone)
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# pcie dma
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self.submodules.pcie_dma = LitePCIeDMA(self.pcie_phy, self.pcie_endpoint,
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with_buffering=True, buffering_depth=1024, with_loopback=True)
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self.add_csr("pcie_dma")
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# DMA0
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self.submodules.pcie_dma0 = LitePCIeDMA(self.pcie_phy, self.pcie_endpoint,
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with_buffering = True, buffering_depth=1024,
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with_loopback = True)
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self.add_csr("pcie_dma0")
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# pcie msi
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# DMA1
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self.submodules.pcie_dma1 = LitePCIeDMA(self.pcie_phy, self.pcie_endpoint,
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with_buffering = True, buffering_depth=1024,
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with_loopback = True)
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self.add_csr("pcie_dma1")
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self.add_constant("DMA_CHANNELS", 2)
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# MSI
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self.submodules.pcie_msi = LitePCIeMSI()
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self.add_csr("pcie_msi")
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self.comb += self.pcie_msi.source.connect(self.pcie_phy.msi)
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self.msis = {
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"DMA_WRITER": self.pcie_dma.writer.irq,
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"DMA_READER": self.pcie_dma.reader.irq
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self.interrupts = {
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"PCIE_DMA0_WRITER": self.pcie_dma0.writer.irq,
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"PCIE_DMA0_READER": self.pcie_dma0.reader.irq,
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"PCIE_DMA1_WRITER": self.pcie_dma1.writer.irq,
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"PCIE_DMA1_READER": self.pcie_dma1.reader.irq,
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}
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for i, (k, v) in enumerate(sorted(self.msis.items())):
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for i, (k, v) in enumerate(sorted(self.interrupts.items())):
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self.comb += self.pcie_msi.irqs[i].eq(v)
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self.add_constant(k + "_INTERRUPT", i)
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def generate_software_header(self, filename):
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csr_header = get_csr_header(self.csr_regions,
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self.constants,
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with_access_functions=False)
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tools.write_to_file(filename, csr_header)
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def generate_software_headers(self):
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csr_header = get_csr_header(self.csr_regions, self.constants, with_access_functions=False)
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tools.write_to_file("csr.h", csr_header)
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soc_header = get_soc_header(self.constants, with_access_functions=False)
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tools.write_to_file("soc.h", soc_header)
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mem_header = get_mem_header(self.mem_regions)
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tools.write_to_file("mem.h", mem_header)
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# Build --------------------------------------------------------------------------------------------
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def main():
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parser = argparse.ArgumentParser(description="LiteX SoC on Tagus")
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parser = argparse.ArgumentParser(description="LiteX SoC on Aller")
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builder_args(parser)
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soc_sdram_args(parser)
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args = parser.parse_args()
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args.uart_name = "crossover"
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# Enforce arguments
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args.uart_name = "crossover"
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args.csr_data_width = 32
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platform = aller.Platform()
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soc = PCIeSoC(platform, **soc_sdram_argdict(args))
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builder = Builder(soc, **builder_argdict(args))
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vns = builder.build()
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soc.generate_software_header("csr.h")
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soc.generate_software_headers()
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if __name__ == "__main__":
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main()
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@ -9,14 +9,20 @@ import sys
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from migen import *
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from litex.build.generic_platform import *
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from litex.build import tools
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from litex_boards.platforms import nereid
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from litex.soc.interconnect.csr import *
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from litex.soc.integration.soc_core import *
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from litex.soc.integration.soc_sdram import *
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from litex.soc.integration.builder import *
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from litex.soc.integration.export import *
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from litex.soc.cores.clock import *
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from litex.soc.cores import dna, xadc
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from litex.soc.cores.uart import *
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from litex.soc.integration.cpu_interface import get_csr_header
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from litex.soc.cores.dna import DNA
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from litex.soc.cores.xadc import XADC
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from litex.soc.cores.icap import ICAP
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from litedram.modules import MT8KTF51264
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from litedram.phy import s7ddrphy
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@ -26,17 +32,20 @@ from litepcie.core import LitePCIeEndpoint, LitePCIeMSI
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from litepcie.frontend.dma import LitePCIeDMA
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from litepcie.frontend.wishbone import LitePCIeWishboneBridge
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from litex_boards.platforms import nereid
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# CRG ----------------------------------------------------------------------------------------------
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class CRG(Module):
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class CRG(Module, AutoCSR):
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def __init__(self, platform, sys_clk_freq):
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self.reset = CSR() # FIXME: not used for now
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self.clock_domains.cd_sys = ClockDomain()
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self.clock_domains.cd_sys4x = ClockDomain(reset_less=True)
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self.clock_domains.cd_clk200 = ClockDomain()
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clk100 = platform.request("clk100")
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platform.add_period_constraint(clk100, 1e9/100e6)
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self.submodules.pll = pll = S7PLL()
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self.comb += pll.reset.eq(platform.request("cpu_reset"))
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@ -50,15 +59,13 @@ class CRG(Module):
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# PCIeSoC -----------------------------------------------------------------------------------------
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class PCIeSoC(SoCCore):
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SoCCore.mem_map["csr"] = 0x80000000
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SoCCore.mem_map["rom"] = 0x20000000
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def __init__(self, platform, **kwargs):
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sys_clk_freq = int(100e6)
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# SoCCore --------------------_-------------------------------------------------------------
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# SoCCore ----------------------------------------------------------------------------------
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SoCCore.__init__(self, platform, sys_clk_freq,
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ident = "LiteX SoC on Nereid", ident_version=True,
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ident = "LiteX SoC on Nereid",
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ident_version = True,
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**kwargs)
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# CRG --------------------------------------------------------------------------------------
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@ -66,13 +73,19 @@ class PCIeSoC(SoCCore):
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self.add_csr("crg")
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# DNA --------------------------------------------------------------------------------------
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self.submodules.dna = dna.DNA()
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self.submodules.dna = DNA()
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self.dna.add_timing_constraints(platform, sys_clk_freq, self.crg.cd_sys.clk)
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self.add_csr("dna")
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# XADC -------------------------------------------------------------------------------------
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self.submodules.xadc = xadc.XADC()
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self.submodules.xadc = XADC()
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self.add_csr("xadc")
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# ICAP -------------------------------------------------------------------------------------
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self.submodules.icap = ICAP(platform)
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self.icap.add_timing_constraints(platform, sys_clk_freq, self.crg.cd_sys.clk)
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self.add_csr("icap")
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# DDR3 SDRAM -------------------------------------------------------------------------------
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if not self.integrated_main_ram_size:
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self.submodules.ddrphy = s7ddrphy.K7DDRPHY(platform.request("ddram"),
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@ -92,42 +105,56 @@ class PCIeSoC(SoCCore):
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)
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# PCIe -------------------------------------------------------------------------------------
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# pcie phy
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self.submodules.pcie_phy = S7PCIEPHY(platform, platform.request("pcie_x1"), bar0_size=0x20000)
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# PHY
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self.submodules.pcie_phy = S7PCIEPHY(platform, platform.request("pcie_x1"),
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data_width = 64,
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bar0_size = 0x20000)
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platform.add_false_path_constraints(self.crg.cd_sys.clk, self.pcie_phy.cd_pcie.clk)
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self.add_csr("pcie_phy")
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# pcie endpoint
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# Endpoint
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self.submodules.pcie_endpoint = LitePCIeEndpoint(self.pcie_phy)
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# pcie wishbone bridge
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self.submodules.pcie_wishbone = LitePCIeWishboneBridge(self.pcie_endpoint,
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lambda a: 1, base_address=self.mem_map["csr"])
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self.add_wb_master(self.pcie_wishbone.wishbone)
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# Wishbone bridge
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self.submodules.pcie_bridge = LitePCIeWishboneBridge(self.pcie_endpoint,
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base_address = self.mem_map["csr"])
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self.add_wb_master(self.pcie_bridge.wishbone)
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# pcie dma
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self.submodules.pcie_dma = LitePCIeDMA(self.pcie_phy, self.pcie_endpoint,
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with_buffering=True, buffering_depth=1024, with_loopback=True)
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self.add_csr("pcie_dma")
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# DMA0
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self.submodules.pcie_dma0 = LitePCIeDMA(self.pcie_phy, self.pcie_endpoint,
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with_buffering = True, buffering_depth=1024,
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with_loopback = True)
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self.add_csr("pcie_dma0")
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# pcie msi
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# DMA1
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self.submodules.pcie_dma1 = LitePCIeDMA(self.pcie_phy, self.pcie_endpoint,
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with_buffering = True, buffering_depth=1024,
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with_loopback = True)
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self.add_csr("pcie_dma1")
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self.add_constant("DMA_CHANNELS", 2)
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# MSI
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self.submodules.pcie_msi = LitePCIeMSI()
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self.add_csr("pcie_msi")
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self.comb += self.pcie_msi.source.connect(self.pcie_phy.msi)
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self.msis = {
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"DMA_WRITER": self.pcie_dma.writer.irq,
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"DMA_READER": self.pcie_dma.reader.irq
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self.interrupts = {
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"PCIE_DMA0_WRITER": self.pcie_dma0.writer.irq,
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"PCIE_DMA0_READER": self.pcie_dma0.reader.irq,
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"PCIE_DMA1_WRITER": self.pcie_dma1.writer.irq,
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"PCIE_DMA1_READER": self.pcie_dma1.reader.irq,
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}
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for i, (k, v) in enumerate(sorted(self.msis.items())):
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for i, (k, v) in enumerate(sorted(self.interrupts.items())):
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self.comb += self.pcie_msi.irqs[i].eq(v)
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self.add_constant(k + "_INTERRUPT", i)
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def generate_software_header(self, filename):
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csr_header = get_csr_header(self.csr_regions,
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self.constants,
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with_access_functions=False)
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tools.write_to_file(filename, csr_header)
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def generate_software_headers(self):
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csr_header = get_csr_header(self.csr_regions, self.constants, with_access_functions=False)
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tools.write_to_file("csr.h", csr_header)
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soc_header = get_soc_header(self.constants, with_access_functions=False)
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tools.write_to_file("soc.h", soc_header)
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mem_header = get_mem_header(self.mem_regions)
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tools.write_to_file("mem.h", mem_header)
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# Build --------------------------------------------------------------------------------------------
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@ -137,14 +164,15 @@ def main():
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soc_sdram_args(parser)
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args = parser.parse_args()
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args.uart_name = "crossover"
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# Enforce arguments
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args.uart_name = "crossover"
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args.csr_data_width = 32
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platform = nereid.Platform()
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soc = PCIeSoC(platform, **soc_sdram_argdict(args))
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builder = Builder(soc, **builder_argdict(args))
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vns = builder.build()
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soc.generate_software_header("csr.h")
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soc.generate_software_headers()
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if __name__ == "__main__":
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main()
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@ -9,14 +9,20 @@ import sys
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from migen import *
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from litex.build.generic_platform import *
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from litex.build import tools
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from litex_boards.platforms import tagus
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from litex.soc.interconnect.csr import *
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from litex.soc.integration.soc_core import *
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from litex.soc.integration.soc_sdram import *
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from litex.soc.integration.builder import *
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from litex.soc.integration.export import *
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from litex.soc.cores.clock import *
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from litex.soc.cores import dna, xadc
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from litex.soc.cores.uart import *
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from litex.soc.integration.cpu_interface import get_csr_header
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from litex.soc.cores.dna import DNA
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from litex.soc.cores.xadc import XADC
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from litex.soc.cores.icap import ICAP
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from litedram.modules import MT41J128M16
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from litedram.phy import s7ddrphy
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@ -26,18 +32,19 @@ from litepcie.core import LitePCIeEndpoint, LitePCIeMSI
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from litepcie.frontend.dma import LitePCIeDMA
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from litepcie.frontend.wishbone import LitePCIeWishboneBridge
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from litex_boards.platforms import tagus
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||||
|
||||
# CRG ----------------------------------------------------------------------------------------------
|
||||
|
||||
class CRG(Module):
|
||||
class CRG(Module, AutoCSR):
|
||||
def __init__(self, platform, sys_clk_freq):
|
||||
self.reset = CSR() # FIXME: not used for now
|
||||
|
||||
self.clock_domains.cd_sys = ClockDomain()
|
||||
self.clock_domains.cd_sys4x = ClockDomain(reset_less=True)
|
||||
self.clock_domains.cd_sys4x_dqs = ClockDomain(reset_less=True)
|
||||
self.clock_domains.cd_clk200 = ClockDomain()
|
||||
|
||||
clk100 = platform.request("clk100")
|
||||
platform.add_period_constraint(clk100, 1e9/100e6)
|
||||
|
||||
self.submodules.pll = pll = S7PLL()
|
||||
self.comb += pll.reset.eq(platform.request("rst"))
|
||||
|
|
@ -52,15 +59,13 @@ class CRG(Module):
|
|||
# PCIeSoC -----------------------------------------------------------------------------------------
|
||||
|
||||
class PCIeSoC(SoCCore):
|
||||
SoCCore.mem_map["csr"] = 0x80000000
|
||||
SoCCore.mem_map["rom"] = 0x20000000
|
||||
|
||||
def __init__(self, platform, **kwargs):
|
||||
sys_clk_freq = int(100e6)
|
||||
|
||||
# SoCCore ---------------------------------------------------_------------------------------
|
||||
# SoCCore ----------------------------------------------------------------------------------
|
||||
SoCCore.__init__(self, platform, sys_clk_freq,
|
||||
ident = "LiteX SoC on Tagus", ident_version=True,
|
||||
ident = "LiteX SoC on Tagus",
|
||||
ident_version = True,
|
||||
**kwargs)
|
||||
|
||||
# CRG --------------------------------------------------------------------------------------
|
||||
|
|
@ -68,13 +73,19 @@ class PCIeSoC(SoCCore):
|
|||
self.add_csr("crg")
|
||||
|
||||
# DNA --------------------------------------------------------------------------------------
|
||||
self.submodules.dna = dna.DNA()
|
||||
self.submodules.dna = DNA()
|
||||
self.dna.add_timing_constraints(platform, sys_clk_freq, self.crg.cd_sys.clk)
|
||||
self.add_csr("dna")
|
||||
|
||||
# XADC -------------------------------------------------------------------------------------
|
||||
self.submodules.xadc = xadc.XADC()
|
||||
self.submodules.xadc = XADC()
|
||||
self.add_csr("xadc")
|
||||
|
||||
# ICAP -------------------------------------------------------------------------------------
|
||||
self.submodules.icap = ICAP(platform)
|
||||
self.icap.add_timing_constraints(platform, sys_clk_freq, self.crg.cd_sys.clk)
|
||||
self.add_csr("icap")
|
||||
|
||||
# DDR3 SDRAM -------------------------------------------------------------------------------
|
||||
if not self.integrated_main_ram_size:
|
||||
self.submodules.ddrphy = s7ddrphy.A7DDRPHY(platform.request("ddram"),
|
||||
|
|
@ -94,42 +105,56 @@ class PCIeSoC(SoCCore):
|
|||
)
|
||||
|
||||
# PCIe -------------------------------------------------------------------------------------
|
||||
# pcie phy
|
||||
self.submodules.pcie_phy = S7PCIEPHY(platform, platform.request("pcie_x1"), bar0_size=0x20000)
|
||||
# PHY
|
||||
self.submodules.pcie_phy = S7PCIEPHY(platform, platform.request("pcie_x1"),
|
||||
data_width = 64,
|
||||
bar0_size = 0x20000)
|
||||
platform.add_false_path_constraints(self.crg.cd_sys.clk, self.pcie_phy.cd_pcie.clk)
|
||||
self.add_csr("pcie_phy")
|
||||
|
||||
# pcie endpoint
|
||||
# Endpoint
|
||||
self.submodules.pcie_endpoint = LitePCIeEndpoint(self.pcie_phy)
|
||||
|
||||
# pcie wishbone bridge
|
||||
self.submodules.pcie_wishbone = LitePCIeWishboneBridge(self.pcie_endpoint,
|
||||
lambda a: 1, base_address=self.mem_map["csr"])
|
||||
self.add_wb_master(self.pcie_wishbone.wishbone)
|
||||
# Wishbone bridge
|
||||
self.submodules.pcie_bridge = LitePCIeWishboneBridge(self.pcie_endpoint,
|
||||
base_address = self.mem_map["csr"])
|
||||
self.add_wb_master(self.pcie_bridge.wishbone)
|
||||
|
||||
# pcie dma
|
||||
self.submodules.pcie_dma = LitePCIeDMA(self.pcie_phy, self.pcie_endpoint,
|
||||
with_buffering=True, buffering_depth=1024, with_loopback=True)
|
||||
self.add_csr("pcie_dma")
|
||||
# DMA0
|
||||
self.submodules.pcie_dma0 = LitePCIeDMA(self.pcie_phy, self.pcie_endpoint,
|
||||
with_buffering = True, buffering_depth=1024,
|
||||
with_loopback = True)
|
||||
self.add_csr("pcie_dma0")
|
||||
|
||||
# pcie msi
|
||||
# DMA1
|
||||
self.submodules.pcie_dma1 = LitePCIeDMA(self.pcie_phy, self.pcie_endpoint,
|
||||
with_buffering = True, buffering_depth=1024,
|
||||
with_loopback = True)
|
||||
self.add_csr("pcie_dma1")
|
||||
|
||||
self.add_constant("DMA_CHANNELS", 2)
|
||||
|
||||
# MSI
|
||||
self.submodules.pcie_msi = LitePCIeMSI()
|
||||
self.add_csr("pcie_msi")
|
||||
self.comb += self.pcie_msi.source.connect(self.pcie_phy.msi)
|
||||
self.msis = {
|
||||
"DMA_WRITER": self.pcie_dma.writer.irq,
|
||||
"DMA_READER": self.pcie_dma.reader.irq
|
||||
self.interrupts = {
|
||||
"PCIE_DMA0_WRITER": self.pcie_dma0.writer.irq,
|
||||
"PCIE_DMA0_READER": self.pcie_dma0.reader.irq,
|
||||
"PCIE_DMA1_WRITER": self.pcie_dma1.writer.irq,
|
||||
"PCIE_DMA1_READER": self.pcie_dma1.reader.irq,
|
||||
}
|
||||
for i, (k, v) in enumerate(sorted(self.msis.items())):
|
||||
for i, (k, v) in enumerate(sorted(self.interrupts.items())):
|
||||
self.comb += self.pcie_msi.irqs[i].eq(v)
|
||||
self.add_constant(k + "_INTERRUPT", i)
|
||||
|
||||
def generate_software_header(self, filename):
|
||||
csr_header = get_csr_header(self.csr_regions,
|
||||
self.constants,
|
||||
with_access_functions=False)
|
||||
tools.write_to_file(filename, csr_header)
|
||||
|
||||
def generate_software_headers(self):
|
||||
csr_header = get_csr_header(self.csr_regions, self.constants, with_access_functions=False)
|
||||
tools.write_to_file("csr.h", csr_header)
|
||||
soc_header = get_soc_header(self.constants, with_access_functions=False)
|
||||
tools.write_to_file("soc.h", soc_header)
|
||||
mem_header = get_mem_header(self.mem_regions)
|
||||
tools.write_to_file("mem.h", mem_header)
|
||||
|
||||
# Build --------------------------------------------------------------------------------------------
|
||||
|
||||
|
|
@ -139,14 +164,15 @@ def main():
|
|||
soc_sdram_args(parser)
|
||||
args = parser.parse_args()
|
||||
|
||||
args.uart_name = "crossover"
|
||||
# Enforce arguments
|
||||
args.uart_name = "crossover"
|
||||
args.csr_data_width = 32
|
||||
|
||||
platform = tagus.Platform()
|
||||
soc = PCIeSoC(platform, **soc_sdram_argdict(args))
|
||||
builder = Builder(soc, **builder_argdict(args))
|
||||
vns = builder.build()
|
||||
soc.generate_software_header("csr.h")
|
||||
soc.generate_software_headers()
|
||||
|
||||
if __name__ == "__main__":
|
||||
main()
|
||||
|
|
|
|||
Loading…
Reference in a new issue