Merge pull request #345 from sergachev/feature/xilinx_kv260
Add Xilinx KV260 support
This commit is contained in:
enjoy-digital
GitHub
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8621700916
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#
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# This file is part of LiteX-Boards.
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#
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# Copyright (c) 2022 Ilia Sergachev <ilia@sergachev.ch>
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# SPDX-License-Identifier: BSD-2-Clause
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from litex.build.generic_platform import *
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from litex.build.xilinx import XilinxPlatform, VivadoProgrammer
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_io = [
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("fan", 0, Pins("A12"), IOStandard("LVCMOS33")),
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# seems like there are no on-board clock sources for PL when PS is not used
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# so here a clock-capable PMOD connector pin is added as a possible clock input (not tested)
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("pmod_hda16_cc", 0, Pins("B21"), IOStandard("LVCMOS33")),
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]
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class Platform(XilinxPlatform):
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default_clk_name = 'pmod_hda16_cc'
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default_clk_period = 10.0
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def __init__(self):
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XilinxPlatform.__init__(self, "xck26-sfvc784-2lv-c", _io, toolchain="vivado")
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self.toolchain.bitstream_commands = \
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["set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]", ]
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self.default_clk_freq = 1e9 / self.default_clk_period
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def create_programmer(self):
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return VivadoProgrammer()
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def do_finalize(self, fragment, *args, **kwargs):
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XilinxPlatform.do_finalize(self, fragment, *args, **kwargs)
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self.add_period_constraint(self.lookup_request("pmod_hda16_cc", loose=True), self.default_clk_period)
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#!/usr/bin/env python3
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#
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# This file is part of LiteX-Boards.
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#
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# Copyright (c) 2022 Ilia Sergachev <ilia@sergachev.ch>
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# SPDX-License-Identifier: BSD-2-Clause
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import argparse
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from migen import *
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from litex_boards.platforms import xilinx_kv260
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from litex.build.xilinx.vivado import vivado_build_args, vivado_build_argdict
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from litex.build.tools import write_to_file
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from litex.soc.interconnect import axi
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from litex.soc.interconnect import wishbone
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from litex.soc.cores.clock import *
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from litex.soc.integration.soc_core import *
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from litex.soc.integration.soc import SoCRegion
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from litex.soc.integration.builder import *
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# CRG ----------------------------------------------------------------------------------------------
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class _CRG(Module):
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def __init__(self, platform, sys_clk_freq, use_ps7_clk=False):
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self.rst = Signal()
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self.clock_domains.cd_sys = ClockDomain()
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# # #
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if use_ps7_clk:
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self.comb += ClockSignal("sys").eq(ClockSignal("ps"))
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self.comb += ResetSignal("sys").eq(ResetSignal("ps") | self.rst)
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else:
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self.submodules.pll = pll = S7PLL(speedgrade=-1)
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self.comb += pll.reset.eq(self.rst)
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pll.register_clkin(platform.request(platform.default_clk_name), platform.default_clk_freq)
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pll.create_clkout(self.cd_sys, sys_clk_freq)
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# Ignore sys_clk to pll.clkin path created by SoC's rst.
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platform.add_false_path_constraints(self.cd_sys.clk, pll.clkin)
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# BaseSoC ------------------------------------------------------------------------------------------
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class BaseSoC(SoCCore):
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mem_map = {"csr": 0xA000_0000} # default GP0 address on ZynqMP
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def __init__(self, sys_clk_freq, **kwargs):
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platform = xilinx_kv260.Platform()
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if kwargs.get("cpu_type", None) == "zynqmp":
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kwargs['integrated_sram_size'] = 0
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# SoCCore ----------------------------------------------------------------------------------
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SoCCore.__init__(self, platform, sys_clk_freq,
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ident = "LiteX SoC on KV260",
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**kwargs)
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# ZynqMP Integration ---------------------------------------------------------------------
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if kwargs.get("cpu_type", None) == "zynqmp":
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self.cpu.config.update({
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'PSU_MIO_36_DIRECTION': 'out',
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'PSU_MIO_37_DIRECTION': 'in',
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'PSU__UART1__BAUD_RATE': 115200,
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'PSU__CRL_APB__UART1_REF_CTRL__DIVISOR0': 10,
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})
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# generated from board xml presets
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self.cpu.config.update({
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'PSU__CRF_APB__ACPU_CTRL__FREQMHZ': '1333.333',
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'PSU__DDRC__BANK_ADDR_COUNT': '2',
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'PSU__DDRC__BG_ADDR_COUNT': '1',
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'PSU__DDRC__BRC_MAPPING': 'ROW_BANK_COL',
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'PSU__DDRC__BUS_WIDTH': '64 Bit',
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'PSU__DDRC__CL': '16',
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'PSU__DDRC__CLOCK_STOP_EN': '0',
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'PSU__DDRC__COL_ADDR_COUNT': '10',
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'PSU__DDRC__COMPONENTS': 'Components',
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'PSU__DDRC__CWL': '12',
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'PSU__DDRC__DDR4_ADDR_MAPPING': '0',
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'PSU__DDRC__DDR4_CAL_MODE_ENABLE': '0',
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'PSU__DDRC__DDR4_CRC_CONTROL': '0',
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'PSU__DDRC__DDR4_T_REF_MODE': '0',
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'PSU__DDRC__DDR4_T_REF_RANGE': 'Normal (0-85)',
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'PSU__DDRC__DEVICE_CAPACITY': '8192 MBits',
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'PSU__DDRC__DIMM_ADDR_MIRROR': '0',
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'PSU__DDRC__DM_DBI': 'DM_NO_DBI',
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'PSU__DDRC__DRAM_WIDTH': '16 Bits',
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'PSU__DDRC__ECC': 'Disabled',
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'PSU__DDRC__FGRM': '1X',
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'PSU__DDRC__LP_ASR': 'manual normal',
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'PSU__DDRC__MEMORY_TYPE': 'DDR 4',
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'PSU__DDRC__PARITY_ENABLE': '0',
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'PSU__DDRC__PER_BANK_REFRESH': '0',
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'PSU__DDRC__PHY_DBI_MODE': '0',
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'PSU__DDRC__RANK_ADDR_COUNT': '0',
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'PSU__DDRC__ROW_ADDR_COUNT': '16',
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'PSU__DDRC__SELF_REF_ABORT': '0',
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'PSU__DDRC__SPEED_BIN': 'DDR4_2400R',
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'PSU__DDRC__STATIC_RD_MODE': '0',
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'PSU__DDRC__TRAIN_DATA_EYE': '1',
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'PSU__DDRC__TRAIN_READ_GATE': '1',
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'PSU__DDRC__TRAIN_WRITE_LEVEL': '1',
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'PSU__DDRC__T_FAW': '30.0',
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'PSU__DDRC__T_RAS_MIN': '33',
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'PSU__DDRC__T_RC': '47.06',
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'PSU__DDRC__T_RCD': '16',
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'PSU__DDRC__T_RP': '16',
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'PSU__DDRC__VREF': '1',
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'PSU__FPGA_PL0_ENABLE': '1',
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'PSU__PMU__GPO4__ENABLE': '0', # these 2 are disabled for uart1
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'PSU__PMU__GPO5__ENABLE': '0',
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'PSU__UART1__PERIPHERAL__ENABLE': '1',
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'PSU__UART1__PERIPHERAL__IO': 'MIO 36 .. 37',
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})
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# Connect Zynq AXI master to the SoC
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wb_gp0 = wishbone.Interface()
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self.submodules += axi.AXI2Wishbone(
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axi = self.cpu.add_axi_gp_master(),
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wishbone = wb_gp0,
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base_address = self.mem_map["csr"])
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self.add_wb_master(wb_gp0)
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self.bus.add_region("sram", SoCRegion(
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origin=self.cpu.mem_map["sram"],
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size=2 * 1024 * 1024 * 1024) # DDR
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)
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self.bus.add_region("rom", SoCRegion(
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origin=self.cpu.mem_map["rom"],
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size=512 * 1024 * 1024 // 8,
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linker=True)
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)
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self.constants['CONFIG_CLOCK_FREQUENCY'] = 1333333008
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use_ps7_clk = True
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else:
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use_ps7_clk = False
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# CRG --------------------------------------------------------------------------------------
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self.submodules.crg = _CRG(platform, sys_clk_freq, use_ps7_clk)
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def finalize(self, *args, **kwargs):
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super(BaseSoC, self).finalize(*args, **kwargs)
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if self.cpu_type != "zynqmp":
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return
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libxil_path = os.path.join(self.builder.software_dir, 'libxil')
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os.makedirs(os.path.realpath(libxil_path), exist_ok=True)
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lib = os.path.join(libxil_path, 'embeddedsw')
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if not os.path.exists(lib):
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os.system("git clone --depth 1 https://github.com/Xilinx/embeddedsw {}".format(lib))
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os.makedirs(os.path.realpath(self.builder.include_dir), exist_ok=True)
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for header in [
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'XilinxProcessorIPLib/drivers/uartps/src/xuartps_hw.h',
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'lib/bsp/standalone/src/common/xil_types.h',
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'lib/bsp/standalone/src/common/xil_assert.h',
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'lib/bsp/standalone/src/common/xil_io.h',
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'lib/bsp/standalone/src/common/xil_printf.h',
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'lib/bsp/standalone/src/common/xstatus.h',
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'lib/bsp/standalone/src/common/xdebug.h',
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'lib/bsp/standalone/src/arm/ARMv8/64bit/xpseudo_asm.h',
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'lib/bsp/standalone/src/arm/ARMv8/64bit/xreg_cortexa53.h',
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'lib/bsp/standalone/src/arm/ARMv8/64bit/xil_cache.h',
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'lib/bsp/standalone/src/arm/ARMv8/64bit/xil_errata.h',
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'lib/bsp/standalone/src/arm/ARMv8/64bit/platform/ZynqMP/xparameters_ps.h',
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'lib/bsp/standalone/src/arm/common/xil_exception.h',
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'lib/bsp/standalone/src/arm/common/gcc/xpseudo_asm_gcc.h',
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]:
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shutil.copy(os.path.join(lib, header), self.builder.include_dir)
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write_to_file(os.path.join(self.builder.include_dir, 'bspconfig.h'), """
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#ifndef BSPCONFIG_H
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#define BSPCONFIG_H
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#define EL3 1
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#define EL1_NONSECURE 0
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#endif
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""")
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write_to_file(os.path.join(self.builder.include_dir, 'xparameters.h'), '''
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#ifndef XPARAMETERS_H
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#define XPARAMETERS_H
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#include "xparameters_ps.h"
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#define STDIN_BASEADDRESS 0xFF010000
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#define STDOUT_BASEADDRESS 0xFF010000
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#define XPAR_PSU_DDR_0_S_AXI_BASEADDR 0x00000000
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#define XPAR_PSU_DDR_0_S_AXI_HIGHADDR 0x7FFFFFFF
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#define XPAR_PSU_DDR_1_S_AXI_BASEADDR 0x800000000
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#define XPAR_PSU_DDR_1_S_AXI_HIGHADDR 0x87FFFFFFF
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#define XPAR_CPU_CORTEXA53_0_TIMESTAMP_CLK_FREQ 99999001
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#endif
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''')
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# Build --------------------------------------------------------------------------------------------
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def main():
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parser = argparse.ArgumentParser(description="LiteX SoC on KV260")
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parser.add_argument("--build", action="store_true", help="Build bitstream.")
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parser.add_argument("--load", action="store_true", help="Load bitstream.")
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parser.add_argument("--sys-clk-freq", default=100e6, help="System clock frequency.")
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builder_args(parser)
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soc_core_args(parser)
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vivado_build_args(parser)
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parser.set_defaults(cpu_type="zynqmp")
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parser.set_defaults(no_uart=True)
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args = parser.parse_args()
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soc = BaseSoC(
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sys_clk_freq=int(float(args.sys_clk_freq)),
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**soc_core_argdict(args)
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)
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builder = Builder(soc, **builder_argdict(args))
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if args.cpu_type == "zynqmp":
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soc.builder = builder
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builder.add_software_package('libxil')
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builder.add_software_library('libxil')
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builder.build(**vivado_build_argdict(args), run=args.build)
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if args.load:
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prog = soc.platform.create_programmer()
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prog.load_bitstream(os.path.join(builder.gateware_dir, soc.build_name + ".bit"))
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if __name__ == "__main__":
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main()
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