platforms/vcu118: rename ddram_second_channel to ddram:1.

2020-05-05 09:54:11 +02:00 · 2020-05-05 09:54:11 +02:00 · 86648ec7d8
parent e1820c7831
commit 86648ec7d8
1 changed files with 1 additions and 1 deletions
--- a/litex_boards/platforms/vcu118.py
+++ b/litex_boards/platforms/vcu118.py
@ -112,7 +112,7 @@ _io = [
    ),

    # DDR4 memory channel C2.
-    ("ddram_second_channel", 0,
+    ("ddram", 1,
        Subsignal("a", Pins(
            "AM27 AL27 AP26 AP25 AN28 AM28 AP28 AP27",
            "AN26 AM26 AR28 AR27 AV25 AT25"),