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versa_ecp5, trellisboard: add trellis toolchain specific arguments

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Sync up with Litex commit #49372852d.
This commit is contained in:
Gabriel Somlo 2019-10-29 12:29:47 -04:00
parent 5f80633154
commit 8878c0a84a
2 changed files with 8 additions and 2 deletions
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5
litex_boards/official/targets/versa_ecp5.py
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@ -11,6 +11,8 @@ from migen.genlib.resetsync import AsyncResetSynchronizer
from litex_boards.platforms import versa_ecp5
from litex.build.lattice.trellis import trellis_args, trellis_argdict
from litex.soc.cores.clock import *
from litex.soc.integration.soc_sdram import *
from litex.soc.integration.builder import *
@ -133,6 +135,7 @@ def main():
help='gateware toolchain to use, diamond (default) or trellis')
builder_args(parser)
soc_sdram_args(parser)
trellis_args(parser)
parser.add_argument("--sys-clk-freq", default=75e6,
help="system clock frequency (default=75MHz)")
parser.add_argument("--with-ethernet", action="store_true",
@ -142,7 +145,7 @@ def main():
cls = EthernetSoC if args.with_ethernet else BaseSoC
soc = cls(toolchain=args.toolchain, sys_clk_freq=int(float(args.sys_clk_freq)), **soc_sdram_argdict(args))
builder = Builder(soc, **builder_argdict(args))
builder.build()
builder.build(**trellis_argdict(args))
if __name__ == "__main__":
main()

5
litex_boards/partner/targets/trellisboard.py
View file

@ -10,6 +10,8 @@ from migen.genlib.resetsync import AsyncResetSynchronizer
from litex_boards.platforms import trellisboard
from litex.build.lattice.trellis import trellis_args, trellis_argdict
from litex.soc.cores.clock import *
from litex.soc.integration.soc_sdram import *
from litex.soc.integration.builder import *
@ -135,6 +137,7 @@ def main():
help='gateware toolchain to use, diamond (default) or trellis')
builder_args(parser)
soc_sdram_args(parser)
trellis_args(parser)
parser.add_argument("--sys-clk-freq", default=75e6,
help="system clock frequency (default=75MHz)")
parser.add_argument("--with-ethernet", action="store_true",
@ -144,7 +147,7 @@ def main():
cls = EthernetSoC if args.with_ethernet else BaseSoC
soc = cls(toolchain=args.toolchain, sys_clk_freq=int(float(args.sys_clk_freq)), **soc_sdram_argdict(args))
builder = Builder(soc, **builder_argdict(args))
builder.build()
builder.build(**trellis_argdict(args))
if __name__ == "__main__":
main()