partner/orange_crab: cleanup, make it similar to others targets and only keep BaseSoC
This commit is contained in:
Florent Kermarrec
parent
e77afaaef0
commit
8965b01347
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@ -7,14 +7,13 @@ from litex.build.lattice import LatticePlatform
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# IOs ----------------------------------------------------------------------------------------------
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_io = [
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("clk100", 0, Pins("A9"), IOStandard("LVCMOS33")),
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("rst_n", 0, Pins("R16"), IOStandard("LVCMOS25")),
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("clk48", 0, Pins("A9"), IOStandard("LVCMOS33")),
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("rgb_led", 0,
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Subsignal("r", Pins("V17"), IOStandard("LVCMOS25")),
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Subsignal("g", Pins("T17"), IOStandard("LVCMOS25")),
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Subsignal("b", Pins("J3"), IOStandard("LVCMOS33")),
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)
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),
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("serial", 0,
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Subsignal("tx", Pins("N17"), IOStandard("LVCMOS25")),
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@ -25,52 +24,32 @@ _io = [
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Subsignal("a", Pins(
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"A4 D2 C3 C7 D3 D4 D1 B2",
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"C1 A2 A7 C2 C4"),
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IOStandard("SSTL135_I"),Misc("SLEWRATE=FAST")),
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Subsignal("ba", Pins("B6 B7 A6"), IOStandard("SSTL135_I"),Misc("SLEWRATE=FAST")),
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Subsignal("ras_n", Pins("C12"), IOStandard("SSTL135_I"),Misc("SLEWRATE=FAST")),
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Subsignal("cas_n", Pins("D13"), IOStandard("SSTL135_I"),Misc("SLEWRATE=FAST")),
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Subsignal("we_n", Pins("B12"), IOStandard("SSTL135_I"),Misc("SLEWRATE=FAST")),
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Subsignal("cs_n", Pins("A12"), IOStandard("SSTL135_I"),Misc("SLEWRATE=FAST")),
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Subsignal("dm", Pins("D16 G16"), IOStandard("SSTL135_I"),Misc("SLEWRATE=FAST")),
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IOStandard("SSTL135_I")),
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Subsignal("ba", Pins("B6 B7 A6"), IOStandard("SSTL135_I")),
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Subsignal("ras_n", Pins("C12"), IOStandard("SSTL135_I")),
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Subsignal("cas_n", Pins("D13"), IOStandard("SSTL135_I")),
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Subsignal("we_n", Pins("B12"), IOStandard("SSTL135_I")),
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Subsignal("cs_n", Pins("A12"), IOStandard("SSTL135_I")),
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Subsignal("dm", Pins("D16 G16"), IOStandard("SSTL135_I")),
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Subsignal("dq", Pins(
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"C17 D15 B17 C16 A15 B13 A17 A13",
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"F17 F16 G15 F15 J16 C18 H16 F18"),
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IOStandard("SSTL135_I"),
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Misc("TERMINATION=75 SLEWRATE=FAST")),
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Subsignal("dqs_p", Pins("B15 G18"), IOStandard("SSTL135D_I"), Misc("TERMINATION=OFF DIFFRESISTOR=100 SLEWRATE=FAST")),
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Subsignal("clk_p", Pins("J18"), IOStandard("SSTL135D_I"),Misc("SLEWRATE=FAST")),
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Subsignal("cke", Pins("D6"), IOStandard("SSTL135_I"),Misc("SLEWRATE=FAST")),
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Subsignal("odt", Pins("C13"), IOStandard("SSTL135_I"),Misc("SLEWRATE=FAST")),
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Subsignal("reset_n", Pins("B1"), IOStandard("SSTL135_I"),Misc("SLEWRATE=FAST")),
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Subsignal("vccio", Pins("D18 K16 B18 D17 K15 K17 C6 A3"), IOStandard("SSTL135_II"), Misc("DRIVE=10")),
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Subsignal("gnd", Pins("L18 L15 L16"), IOStandard("SSTL135_II"), Misc("DRIVE=10")),
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Misc("TERMINATION=75")),
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Subsignal("dqs_p", Pins("B15 G18"), IOStandard("SSTL135D_I"), Misc("TERMINATION=OFF DIFFRESISTOR=100")),
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Subsignal("clk_p", Pins("J18"), IOStandard("SSTL135D_I")),
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Subsignal("cke", Pins("D6"), IOStandard("SSTL135_I")),
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Subsignal("odt", Pins("C13"), IOStandard("SSTL135_I")),
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Subsignal("reset_n", Pins("B1"), IOStandard("SSTL135_I")),
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Misc("SLEWRATE=FAST")
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),
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("spiflash4x", 0,
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Subsignal("cs_n", Pins("U17")),
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Subsignal("clk", Pins("U16")),
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Subsignal("dq", Pins("U18", "T18", "R18", "N18")),
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IOStandard("LVCMOS25")
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),
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#("spiflash", 0,
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# Subsignal("cs_n", Pins("U17")),
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# Subsignal("clk", Pins("U16")),
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# Subsignal("mosi", Pins("U18")),
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# Subsignal("miso", Pins("T18")),
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# Subsignal("wp", Pins("R18")),
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# Subsignal("hold", Pins("N18")),
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# IOStandard("LVCMOS25"),
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#),
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]
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# Connectors ---------------------------------------------------------------------------------------
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_connectors = [
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]
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# Platform -----------------------------------------------------------------------------------------
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@ -80,5 +59,4 @@ class Platform(LatticePlatform):
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default_clk_period = int(1e9/48e6)
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def __init__(self, **kwargs):
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LatticePlatform.__init__(self, "LFE5U-25F-8MG285C", _io, _connectors, **kwargs)
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LatticePlatform.__init__(self, "LFE5U-25F-8MG285C", _io, **kwargs)
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@ -3,39 +3,31 @@
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# This file is Copyright (c) Greg Davill <greg.davill@gmail.com>
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# License: BSD
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import sys
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import argparse
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from migen import *
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from migen.genlib.resetsync import AsyncResetSynchronizer
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from litex.build.generic_platform import *
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from litex_boards.platforms import orange_crab
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from litex.build.lattice.trellis import trellis_args, trellis_argdict
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from litex.soc.cores.clock import *
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from litex.soc.integration.soc_core import *
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from litex.soc.integration.soc_sdram import *
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from litex.soc.integration.builder import *
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from litex.soc.cores.uart import UARTWishboneBridge
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from litex.soc.interconnect import wishbone
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from litedram.modules import MT41K64M16
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from .ecp5ddrphy import ECP5DDRPHY, ECP5DDRPHYInit
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from litedram.init import get_sdram_phy_py_header
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from litedram.frontend.bist import LiteDRAMBISTGenerator
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from litedram.frontend.bist import LiteDRAMBISTChecker
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from litedram.phy import ECP5DDRPHY
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# _CRG ---------------------------------------------------------------------------------------------
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# DDR3TestCRG --------------------------------------------------------------------------------------
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class DDR3TestCRG(Module):
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class _CRG(Module):
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def __init__(self, platform, sys_clk_freq):
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self.clock_domains.cd_init = ClockDomain()
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self.clock_domains.cd_por = ClockDomain(reset_less=True)
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self.clock_domains.cd_sys = ClockDomain()
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self.clock_domains.cd_sys2x = ClockDomain()
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self.clock_domains.cd_sys2x_i = ClockDomain(reset_less=True)
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self.clock_domains.cd_init = ClockDomain()
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self.clock_domains.cd_por = ClockDomain(reset_less=True)
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self.clock_domains.cd_sys = ClockDomain()
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self.clock_domains.cd_sys2x = ClockDomain()
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self.clock_domains.cd_sys2x_i = ClockDomain(reset_less=True)
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self.clock_domains.cd_sys2x_eb = ClockDomain(reset_less=True)
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@ -44,127 +36,84 @@ class DDR3TestCRG(Module):
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self.stop = Signal()
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# clk / rst
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clk100 = platform.request("clk100")
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#rst_n = platform.request("rst_n")
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rst_n = Signal(reset=1)
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platform.add_period_constraint(clk100, 1e9/48e6)
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clk48 = platform.request("clk48")
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platform.add_period_constraint(clk48, 1e9/48e6)
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# power on reset
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por_count = Signal(16, reset=2**16-1)
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por_done = Signal()
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por_done = Signal()
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self.comb += self.cd_por.clk.eq(ClockSignal())
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self.comb += por_done.eq(por_count == 0)
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self.sync.por += If(~por_done, por_count.eq(por_count - 1))
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# pll
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sys2x_i_clk = Signal()
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sys2x_clk_ecsout = Signal()
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self.submodules.pll = pll = ECP5PLL()
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pll.register_clkin(clk100, 48e6)
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pll.create_clkout(self.cd_sys2x_eb, 2*sys_clk_freq)
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pll.register_clkin(clk48, 48e6)
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pll.create_clkout(self.cd_sys2x_i, 2*sys_clk_freq)
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pll.create_clkout(self.cd_init, 24e6)
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self.specials += [
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Instance("ECLKSYNCB",
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i_ECLKI=sys2x_i_clk,
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i_STOP=self.stop,
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o_ECLKO=self.cd_sys2x.clk),
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Instance("ECLKBRIDGECS",
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i_CLK0=self.cd_sys2x_eb.clk,
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i_SEL=0,
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o_ECSOUT=sys2x_i_clk),
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i_CLK0 = self.cd_sys2x_i.clk,
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i_SEL = 0,
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o_ECSOUT = sys2x_clk_ecsout,
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),
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Instance("ECLKSYNCB",
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i_ECLKI = sys2x_clk_ecsout,
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i_STOP = self.stop,
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o_ECLKO = self.cd_sys2x.clk),
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Instance("CLKDIVF",
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p_DIV="2.0",
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i_ALIGNWD=0,
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i_CLKI=self.cd_sys2x.clk,
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i_RST=self.cd_sys2x.rst,
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o_CDIVX=self.cd_sys.clk),
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AsyncResetSynchronizer(self.cd_init, ~por_done | ~pll.locked | ~rst_n),
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AsyncResetSynchronizer(self.cd_sys, ~por_done | ~pll.locked | ~rst_n)
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p_DIV = "2.0",
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i_ALIGNWD = 0,
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i_CLKI = self.cd_sys2x.clk,
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i_RST = self.cd_sys2x.rst,
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o_CDIVX = self.cd_sys.clk),
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AsyncResetSynchronizer(self.cd_init, ~por_done | ~pll.locked),
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AsyncResetSynchronizer(self.cd_sys, ~por_done | ~pll.locked)
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]
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# BaseSoC ------------------------------------------------------------------------------------------
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class BaseSoC(SoCSDRAM):
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csr_map = {
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"ddrphy": 16,
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}
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csr_map.update(SoCSDRAM.csr_map)
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def __init__(self, toolchain="trellis", integrated_rom_size=0x8000, **kwargs):
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platform = OrangeCrab.Platform(toolchain=toolchain)
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sys_clk_freq = int(48e6)
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def __init__(self, sys_clk_freq=int(48e6), toolchain="diamond", integrated_rom_size=0x8000, **kwargs):
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platform = orange_crab.Platform(toolchain=toolchain)
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# SoCSDRAM ---------------------------------------------------------------------------------
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SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq,
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integrated_rom_size=integrated_rom_size,
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**kwargs)
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# crg
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self.submodules.crg = DDR3TestCRG(platform, sys_clk_freq)
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# CRG --------------------------------------------------------------------------------------
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self.submodules.crg = _CRG(platform, sys_clk_freq)
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# sdram
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# DDR3 SDRAM -------------------------------------------------------------------------------
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self.submodules.ddrphy = ECP5DDRPHY(
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platform.request("ddram"),
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sys_clk_freq=sys_clk_freq)
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self.add_csr("ddrphy")
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self.add_constant("ECP5DDRPHY", None)
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self.comb += self.crg.stop.eq(self.ddrphy.init.stop)
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sdram_module = MT41K64M16(sys_clk_freq, "1:2")
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self.register_sdram(self.ddrphy,
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sdram_module.geom_settings,
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sdram_module.timing_settings)
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# led blinking
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#led_counter = Signal(32)
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#led = platform.request("rgb_led", 0)
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#
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#self.sync += led_counter.eq(led_counter + 1)
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#self.comb += [
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# led.r.eq(led_counter[24]),
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# led.g.eq(led_counter[27]),
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# led.b.eq(led_counter[28])
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#]
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# BISTSoC --------------------------------------------------------------------------------------
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class BISTSoC(BaseSoC):
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csr_map = {
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"sdram_generator": 20,
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"sdram_checker": 21
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}
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csr_map.update(BaseSoC.csr_map)
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def __init__(self, **kwargs):
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BaseSoC.__init__(self, **kwargs)
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self.submodules.sdram_generator = LiteDRAMBISTGenerator(self.sdram.crossbar.get_port())
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self.submodules.sdram_checker = LiteDRAMBISTChecker(self.sdram.crossbar.get_port())
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geom_settings = sdram_module.geom_settings,
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timing_settings = sdram_module.timing_settings)
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# Build --------------------------------------------------------------------------------------------
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def main():
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parser = argparse.ArgumentParser(description="LiteX SoC on OrangeCrab")
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parser.add_argument("--gateware-toolchain", dest="toolchain", default="diamond",
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help='gateware toolchain to use, diamond (default) or trellis')
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builder_args(parser)
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soc_sdram_args(parser)
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trellis_args(parser)
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parser.add_argument("--sys-clk-freq", default=48e6,
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help="system clock frequency (default=48MHz)")
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args = parser.parse_args()
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if "diamond" in sys.argv[1:]:
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toolchain = "diamond"
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toolchain_path = "/usr/local/diamond/3.10_x64/bin/lin64"
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else:
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toolchain = "trellis"
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toolchain_path = "/usr/share/trellis"
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if "ddr3_test" in sys.argv[1:]:
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soc = DDR3TestSoC(toolchain=toolchain)
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elif "base" in sys.argv[1:]:
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soc = BaseSoC(toolchain=toolchain)
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elif "bist" in sys.argv[1:]:
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soc = BISTSoC(toolchain=toolchain)
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else:
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print("missing target, supported: (ddr3_test, base, bist)")
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exit(1)
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builder = Builder(soc, output_dir="build", csr_csv="test/csr.csv")
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vns = builder.build(toolchain_path=toolchain_path)
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if isinstance(soc, DDR3TestSoC):
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soc.do_exit(vns)
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soc.generate_sdram_phy_py_header()
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# Generate svf
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os.system("python3 openocd/bit_to_svf.py build/gateware/top.bit build/gateware/top.svf")
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soc = BaseSoC(toolchain=args.toolchain, sys_clk_freq=int(float(args.sys_clk_freq)), **soc_sdram_argdict(args))
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builder = Builder(soc, **builder_argdict(args))
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builder.build(**trellis_argdict(args))
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if __name__ == "__main__":
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main()
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