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partner/orange_crab: cleanup, make it similar to others targets and only keep BaseSoC

This commit is contained in:
Florent Kermarrec 2019-12-30 11:53:19 +01:00
parent e77afaaef0
commit 8965b01347
2 changed files with 69 additions and 142 deletions
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54
litex_boards/partner/platforms/orange_crab.py
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@ -7,14 +7,13 @@ from litex.build.lattice import LatticePlatform
# IOs ---------------------------------------------------------------------------------------------- # IOs ----------------------------------------------------------------------------------------------
_io = [ _io = [
("clk100", 0, Pins("A9"), IOStandard("LVCMOS33")), ("clk48", 0, Pins("A9"), IOStandard("LVCMOS33")),
("rst_n", 0, Pins("R16"), IOStandard("LVCMOS25")),
("rgb_led", 0, ("rgb_led", 0,
Subsignal("r", Pins("V17"), IOStandard("LVCMOS25")), Subsignal("r", Pins("V17"), IOStandard("LVCMOS25")),
Subsignal("g", Pins("T17"), IOStandard("LVCMOS25")), Subsignal("g", Pins("T17"), IOStandard("LVCMOS25")),
Subsignal("b", Pins("J3"), IOStandard("LVCMOS33")), Subsignal("b", Pins("J3"), IOStandard("LVCMOS33")),
) ),
("serial", 0, ("serial", 0,
Subsignal("tx", Pins("N17"), IOStandard("LVCMOS25")), Subsignal("tx", Pins("N17"), IOStandard("LVCMOS25")),
@ -25,52 +24,32 @@ _io = [
Subsignal("a", Pins( Subsignal("a", Pins(
"A4 D2 C3 C7 D3 D4 D1 B2", "A4 D2 C3 C7 D3 D4 D1 B2",
"C1 A2 A7 C2 C4"), "C1 A2 A7 C2 C4"),
IOStandard("SSTL135_I"),Misc("SLEWRATE=FAST")), IOStandard("SSTL135_I")),
Subsignal("ba", Pins("B6 B7 A6"), IOStandard("SSTL135_I"),Misc("SLEWRATE=FAST")), Subsignal("ba", Pins("B6 B7 A6"), IOStandard("SSTL135_I")),
Subsignal("ras_n", Pins("C12"), IOStandard("SSTL135_I"),Misc("SLEWRATE=FAST")), Subsignal("ras_n", Pins("C12"), IOStandard("SSTL135_I")),
Subsignal("cas_n", Pins("D13"), IOStandard("SSTL135_I"),Misc("SLEWRATE=FAST")), Subsignal("cas_n", Pins("D13"), IOStandard("SSTL135_I")),
Subsignal("we_n", Pins("B12"), IOStandard("SSTL135_I"),Misc("SLEWRATE=FAST")), Subsignal("we_n", Pins("B12"), IOStandard("SSTL135_I")),
Subsignal("cs_n", Pins("A12"), IOStandard("SSTL135_I"),Misc("SLEWRATE=FAST")), Subsignal("cs_n", Pins("A12"), IOStandard("SSTL135_I")),
Subsignal("dm", Pins("D16 G16"), IOStandard("SSTL135_I"),Misc("SLEWRATE=FAST")), Subsignal("dm", Pins("D16 G16"), IOStandard("SSTL135_I")),
Subsignal("dq", Pins( Subsignal("dq", Pins(
"C17 D15 B17 C16 A15 B13 A17 A13", "C17 D15 B17 C16 A15 B13 A17 A13",
"F17 F16 G15 F15 J16 C18 H16 F18"), "F17 F16 G15 F15 J16 C18 H16 F18"),
IOStandard("SSTL135_I"), IOStandard("SSTL135_I"),
Misc("TERMINATION=75 SLEWRATE=FAST")), Misc("TERMINATION=75")),
Subsignal("dqs_p", Pins("B15 G18"), IOStandard("SSTL135D_I"), Misc("TERMINATION=OFF DIFFRESISTOR=100 SLEWRATE=FAST")), Subsignal("dqs_p", Pins("B15 G18"), IOStandard("SSTL135D_I"), Misc("TERMINATION=OFF DIFFRESISTOR=100")),
Subsignal("clk_p", Pins("J18"), IOStandard("SSTL135D_I"),Misc("SLEWRATE=FAST")), Subsignal("clk_p", Pins("J18"), IOStandard("SSTL135D_I")),
Subsignal("cke", Pins("D6"), IOStandard("SSTL135_I"),Misc("SLEWRATE=FAST")), Subsignal("cke", Pins("D6"), IOStandard("SSTL135_I")),
Subsignal("odt", Pins("C13"), IOStandard("SSTL135_I"),Misc("SLEWRATE=FAST")), Subsignal("odt", Pins("C13"), IOStandard("SSTL135_I")),
Subsignal("reset_n", Pins("B1"), IOStandard("SSTL135_I"),Misc("SLEWRATE=FAST")), Subsignal("reset_n", Pins("B1"), IOStandard("SSTL135_I")),
Subsignal("vccio", Pins("D18 K16 B18 D17 K15 K17 C6 A3"), IOStandard("SSTL135_II"), Misc("DRIVE=10")),
Subsignal("gnd", Pins("L18 L15 L16"), IOStandard("SSTL135_II"), Misc("DRIVE=10")),
Misc("SLEWRATE=FAST") Misc("SLEWRATE=FAST")
), ),
("spiflash4x", 0, ("spiflash4x", 0,
Subsignal("cs_n", Pins("U17")), Subsignal("cs_n", Pins("U17")),
Subsignal("clk", Pins("U16")), Subsignal("clk", Pins("U16")),
Subsignal("dq", Pins("U18", "T18", "R18", "N18")), Subsignal("dq", Pins("U18", "T18", "R18", "N18")),
IOStandard("LVCMOS25") IOStandard("LVCMOS25")
), ),
#("spiflash", 0,
# Subsignal("cs_n", Pins("U17")),
# Subsignal("clk", Pins("U16")),
# Subsignal("mosi", Pins("U18")),
# Subsignal("miso", Pins("T18")),
# Subsignal("wp", Pins("R18")),
# Subsignal("hold", Pins("N18")),
# IOStandard("LVCMOS25"),
#),
]
# Connectors ---------------------------------------------------------------------------------------
_connectors = [
] ]
# Platform ----------------------------------------------------------------------------------------- # Platform -----------------------------------------------------------------------------------------
@ -80,5 +59,4 @@ class Platform(LatticePlatform):
default_clk_period = int(1e9/48e6) default_clk_period = int(1e9/48e6)
def __init__(self, **kwargs): def __init__(self, **kwargs):
LatticePlatform.__init__(self, "LFE5U-25F-8MG285C", _io, _connectors, **kwargs) LatticePlatform.__init__(self, "LFE5U-25F-8MG285C", _io, **kwargs)

157
litex_boards/partner/targets/orange_crab.py
View File

@ -3,39 +3,31 @@
# This file is Copyright (c) Greg Davill <greg.davill@gmail.com> # This file is Copyright (c) Greg Davill <greg.davill@gmail.com>
# License: BSD # License: BSD
import sys
import argparse import argparse
from migen import * from migen import *
from migen.genlib.resetsync import AsyncResetSynchronizer from migen.genlib.resetsync import AsyncResetSynchronizer
from litex.build.generic_platform import *
from litex_boards.platforms import orange_crab from litex_boards.platforms import orange_crab
from litex.build.lattice.trellis import trellis_args, trellis_argdict
from litex.soc.cores.clock import * from litex.soc.cores.clock import *
from litex.soc.integration.soc_core import *
from litex.soc.integration.soc_sdram import * from litex.soc.integration.soc_sdram import *
from litex.soc.integration.builder import * from litex.soc.integration.builder import *
from litex.soc.cores.uart import UARTWishboneBridge
from litex.soc.interconnect import wishbone
from litedram.modules import MT41K64M16 from litedram.modules import MT41K64M16
from .ecp5ddrphy import ECP5DDRPHY, ECP5DDRPHYInit from litedram.phy import ECP5DDRPHY
from litedram.init import get_sdram_phy_py_header
from litedram.frontend.bist import LiteDRAMBISTGenerator
from litedram.frontend.bist import LiteDRAMBISTChecker
# _CRG ---------------------------------------------------------------------------------------------
# DDR3TestCRG -------------------------------------------------------------------------------------- class _CRG(Module):
class DDR3TestCRG(Module):
def __init__(self, platform, sys_clk_freq): def __init__(self, platform, sys_clk_freq):
self.clock_domains.cd_init = ClockDomain() self.clock_domains.cd_init = ClockDomain()
self.clock_domains.cd_por = ClockDomain(reset_less=True) self.clock_domains.cd_por = ClockDomain(reset_less=True)
self.clock_domains.cd_sys = ClockDomain() self.clock_domains.cd_sys = ClockDomain()
self.clock_domains.cd_sys2x = ClockDomain() self.clock_domains.cd_sys2x = ClockDomain()
self.clock_domains.cd_sys2x_i = ClockDomain(reset_less=True) self.clock_domains.cd_sys2x_i = ClockDomain(reset_less=True)
self.clock_domains.cd_sys2x_eb = ClockDomain(reset_less=True) self.clock_domains.cd_sys2x_eb = ClockDomain(reset_less=True)
@ -44,127 +36,84 @@ class DDR3TestCRG(Module):
self.stop = Signal() self.stop = Signal()
# clk / rst # clk / rst
clk100 = platform.request("clk100") clk48 = platform.request("clk48")
#rst_n = platform.request("rst_n") platform.add_period_constraint(clk48, 1e9/48e6)
rst_n = Signal(reset=1)
platform.add_period_constraint(clk100, 1e9/48e6)
# power on reset # power on reset
por_count = Signal(16, reset=2**16-1) por_count = Signal(16, reset=2**16-1)
por_done = Signal() por_done = Signal()
self.comb += self.cd_por.clk.eq(ClockSignal()) self.comb += self.cd_por.clk.eq(ClockSignal())
self.comb += por_done.eq(por_count == 0) self.comb += por_done.eq(por_count == 0)
self.sync.por += If(~por_done, por_count.eq(por_count - 1)) self.sync.por += If(~por_done, por_count.eq(por_count - 1))
# pll # pll
sys2x_clk_ecsout = Signal()
sys2x_i_clk = Signal()
self.submodules.pll = pll = ECP5PLL() self.submodules.pll = pll = ECP5PLL()
pll.register_clkin(clk100, 48e6) pll.register_clkin(clk48, 48e6)
pll.create_clkout(self.cd_sys2x_eb, 2*sys_clk_freq) pll.create_clkout(self.cd_sys2x_i, 2*sys_clk_freq)
pll.create_clkout(self.cd_init, 24e6) pll.create_clkout(self.cd_init, 24e6)
self.specials += [ self.specials += [
Instance("ECLKSYNCB",
i_ECLKI=sys2x_i_clk,
i_STOP=self.stop,
o_ECLKO=self.cd_sys2x.clk),
Instance("ECLKBRIDGECS", Instance("ECLKBRIDGECS",
i_CLK0=self.cd_sys2x_eb.clk, i_CLK0 = self.cd_sys2x_i.clk,
i_SEL=0, i_SEL = 0,
o_ECSOUT=sys2x_i_clk), o_ECSOUT = sys2x_clk_ecsout,
),
Instance("ECLKSYNCB",
i_ECLKI = sys2x_clk_ecsout,
i_STOP = self.stop,
o_ECLKO = self.cd_sys2x.clk),
Instance("CLKDIVF", Instance("CLKDIVF",
p_DIV="2.0", p_DIV = "2.0",
i_ALIGNWD=0, i_ALIGNWD = 0,
i_CLKI=self.cd_sys2x.clk, i_CLKI = self.cd_sys2x.clk,
i_RST=self.cd_sys2x.rst, i_RST = self.cd_sys2x.rst,
o_CDIVX=self.cd_sys.clk), o_CDIVX = self.cd_sys.clk),
AsyncResetSynchronizer(self.cd_init, ~por_done | ~pll.locked | ~rst_n), AsyncResetSynchronizer(self.cd_init, ~por_done | ~pll.locked),
AsyncResetSynchronizer(self.cd_sys, ~por_done | ~pll.locked | ~rst_n) AsyncResetSynchronizer(self.cd_sys, ~por_done | ~pll.locked)
] ]
# BaseSoC ------------------------------------------------------------------------------------------ # BaseSoC ------------------------------------------------------------------------------------------
class BaseSoC(SoCSDRAM): class BaseSoC(SoCSDRAM):
csr_map = { def __init__(self, sys_clk_freq=int(48e6), toolchain="diamond", integrated_rom_size=0x8000, **kwargs):
"ddrphy": 16, platform = orange_crab.Platform(toolchain=toolchain)
}
csr_map.update(SoCSDRAM.csr_map) # SoCSDRAM ---------------------------------------------------------------------------------
def __init__(self, toolchain="trellis", integrated_rom_size=0x8000, **kwargs):
platform = OrangeCrab.Platform(toolchain=toolchain)
sys_clk_freq = int(48e6)
SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq, SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq,
integrated_rom_size=integrated_rom_size, integrated_rom_size=integrated_rom_size,
**kwargs) **kwargs)
# crg # CRG --------------------------------------------------------------------------------------
self.submodules.crg = DDR3TestCRG(platform, sys_clk_freq) self.submodules.crg = _CRG(platform, sys_clk_freq)
# sdram # DDR3 SDRAM -------------------------------------------------------------------------------
self.submodules.ddrphy = ECP5DDRPHY( self.submodules.ddrphy = ECP5DDRPHY(
platform.request("ddram"), platform.request("ddram"),
sys_clk_freq=sys_clk_freq) sys_clk_freq=sys_clk_freq)
self.add_csr("ddrphy")
self.add_constant("ECP5DDRPHY", None) self.add_constant("ECP5DDRPHY", None)
self.comb += self.crg.stop.eq(self.ddrphy.init.stop) self.comb += self.crg.stop.eq(self.ddrphy.init.stop)
sdram_module = MT41K64M16(sys_clk_freq, "1:2") sdram_module = MT41K64M16(sys_clk_freq, "1:2")
self.register_sdram(self.ddrphy, self.register_sdram(self.ddrphy,
sdram_module.geom_settings, geom_settings = sdram_module.geom_settings,
sdram_module.timing_settings) timing_settings = sdram_module.timing_settings)
# led blinking
#led_counter = Signal(32)
#led = platform.request("rgb_led", 0)
#
#self.sync += led_counter.eq(led_counter + 1)
#self.comb += [
# led.r.eq(led_counter[24]),
# led.g.eq(led_counter[27]),
# led.b.eq(led_counter[28])
#]
# BISTSoC --------------------------------------------------------------------------------------
class BISTSoC(BaseSoC):
csr_map = {
"sdram_generator": 20,
"sdram_checker": 21
}
csr_map.update(BaseSoC.csr_map)
def __init__(self, **kwargs):
BaseSoC.__init__(self, **kwargs)
self.submodules.sdram_generator = LiteDRAMBISTGenerator(self.sdram.crossbar.get_port())
self.submodules.sdram_checker = LiteDRAMBISTChecker(self.sdram.crossbar.get_port())
# Build -------------------------------------------------------------------------------------------- # Build --------------------------------------------------------------------------------------------
def main(): def main():
parser = argparse.ArgumentParser(description="LiteX SoC on OrangeCrab")
parser.add_argument("--gateware-toolchain", dest="toolchain", default="diamond",
help='gateware toolchain to use, diamond (default) or trellis')
builder_args(parser)
soc_sdram_args(parser)
trellis_args(parser)
parser.add_argument("--sys-clk-freq", default=48e6,
help="system clock frequency (default=48MHz)")
args = parser.parse_args()
if "diamond" in sys.argv[1:]: soc = BaseSoC(toolchain=args.toolchain, sys_clk_freq=int(float(args.sys_clk_freq)), **soc_sdram_argdict(args))
toolchain = "diamond" builder = Builder(soc, **builder_argdict(args))
toolchain_path = "/usr/local/diamond/3.10_x64/bin/lin64" builder.build(**trellis_argdict(args))
else:
toolchain = "trellis"
toolchain_path = "/usr/share/trellis"
if "ddr3_test" in sys.argv[1:]:
soc = DDR3TestSoC(toolchain=toolchain)
elif "base" in sys.argv[1:]:
soc = BaseSoC(toolchain=toolchain)
elif "bist" in sys.argv[1:]:
soc = BISTSoC(toolchain=toolchain)
else:
print("missing target, supported: (ddr3_test, base, bist)")
exit(1)
builder = Builder(soc, output_dir="build", csr_csv="test/csr.csv")
vns = builder.build(toolchain_path=toolchain_path)
if isinstance(soc, DDR3TestSoC):
soc.do_exit(vns)
soc.generate_sdram_phy_py_header()
# Generate svf
os.system("python3 openocd/bit_to_svf.py build/gateware/top.bit build/gateware/top.svf")
if __name__ == "__main__": if __name__ == "__main__":
main() main()