Hardware
/
litex-boards
mirror of https://github.com/litex-hub/litex-boards.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

sitlinv_stlv7325: Rename to v1 and update VCCIO to fix --with-pcie generation.

This commit is contained in:
Florent Kermarrec 2023-05-30 10:39:20 +02:00
parent 2ae2dfa6a3
commit 8a263c18f2
2 changed files with 8 additions and 8 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

8
litex_boards/platforms/sitlinv_stlv7325.py → litex_boards/platforms/sitlinv_stlv7325_v1.py
View File

@ -15,7 +15,7 @@ from litex.build.openocd import OpenOCD
def _get_io(voltage="2.5V"):
assert voltage in ["2.5V", "3.3V"]
VCCIO = str(25 if voltage == "2.5V" else 33)
VCCIO = {"2.5V": "25", "3.3V": "33"}[voltage]
_io = [
# Clk / Rst
("cpu_reset_n", 0, Pins("AC16"), IOStandard("LVCMOS15")),
@ -203,7 +203,7 @@ def _get_io(voltage="2.5V"):
# PCIe
("pcie_x1", 0,
Subsignal("rst_n", Pins("E17"), IOStandard("LVCMOS15")),
Subsignal("rst_n", Pins("E17"), IOStandard("LVCMOS" + VCCIO)),
Subsignal("clk_p", Pins("H6")),
Subsignal("clk_n", Pins("H5")),
Subsignal("rx_p", Pins("B6")),
@ -212,7 +212,7 @@ def _get_io(voltage="2.5V"):
Subsignal("tx_n", Pins("A3"))
),
("pcie_x2", 0,
Subsignal("rst_n", Pins("E17"), IOStandard("LVCMOS15")),
Subsignal("rst_n", Pins("E17"), IOStandard("LVCMOS" + VCCIO)),
Subsignal("clk_p", Pins("H6")),
Subsignal("clk_n", Pins("H5")),
Subsignal("rx_p", Pins("B6 C4")),
@ -221,7 +221,7 @@ def _get_io(voltage="2.5V"):
Subsignal("tx_n", Pins("A3 B1"))
),
("pcie_x4", 0,
Subsignal("rst_n", Pins("E17"), IOStandard("LVCMOS15")),
Subsignal("rst_n", Pins("E17"), IOStandard("LVCMOS" + VCCIO)),
Subsignal("clk_p", Pins("H6")),
Subsignal("clk_n", Pins("H5")),
Subsignal("rx_p", Pins("B6 C4 E4 G4")),

8
litex_boards/targets/sitlinv_stlv7325.py → litex_boards/targets/sitlinv_stlv7325_v1.py
View File

@ -15,7 +15,7 @@ from migen import *
from litex.gen import *
from litex_boards.platforms import sitlinv_stlv7325
from litex_boards.platforms import sitlinv_stlv7325_v1
from litex.soc.cores.clock import *
from litex.soc.integration.soc_core import *
@ -85,13 +85,13 @@ class BaseSoC(SoCCore):
with_video_framebuffer = False,
with_video_terminal = False,
**kwargs):
platform = sitlinv_stlv7325.Platform(vccio)
platform = sitlinv_stlv7325_v1.Platform(vccio)
# CRG --------------------------------------------------------------------------------------
self.crg = _CRG(platform, sys_clk_freq)
# SoCCore ----------------------------------------------------------------------------------
SoCCore.__init__(self, platform, sys_clk_freq, ident="LiteX SoC on Sitlinv STLV7325", **kwargs)
SoCCore.__init__(self, platform, sys_clk_freq, ident="LiteX SoC on Sitlinv STLV7325-V1", **kwargs)
# DDR3 SDRAM -------------------------------------------------------------------------------
if not self.integrated_main_ram_size:
@ -188,7 +188,7 @@ class BaseSoC(SoCCore):
def main():
from litex.build.parser import LiteXArgumentParser
parser = LiteXArgumentParser(platform=sitlinv_stlv7325.Platform, description="LiteX SoC on AliExpress STLV7325.")
parser = LiteXArgumentParser(platform=sitlinv_stlv7325_v1.Platform, description="LiteX SoC on Sitlinv STLV7325-V1.")
parser.add_target_argument("--sys-clk-freq", default=100e6, type=float, help="System clock frequency.")
parser.add_target_argument("--vccio", default="2.5V", type=str, help="IO Voltage (set by J4), can be 2.5V or 3.3V")
ethopts = parser.target_group.add_mutually_exclusive_group()