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fairwaves_xtrx: Add pcie_x2 definitions and switch to it.

This commit is contained in:
Florent Kermarrec 2021-12-07 15:27:55 +01:00
parent df175c5750
commit 8ad89881c2
2 changed files with 6 additions and 6 deletions
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10
litex_boards/platforms/fairwaves_xtrx.py
View File

@ -20,14 +20,14 @@ _io = [
("user_led", 0, Pins("N18"), IOStandard("LVCMOS25")), ("user_led", 0, Pins("N18"), IOStandard("LVCMOS25")),
# PCIe. # PCIe.
("pcie_x1", 0, ("pcie_x2", 0,
Subsignal("rst_n", Pins("T3"), IOStandard("LVCMOS25"), Misc("PULLUP=TRUE")), Subsignal("rst_n", Pins("T3"), IOStandard("LVCMOS25"), Misc("PULLUP=TRUE")),
Subsignal("clk_p", Pins("B8")), Subsignal("clk_p", Pins("B8")),
Subsignal("clk_n", Pins("A8")), Subsignal("clk_n", Pins("A8")),
Subsignal("rx_p", Pins("B10")), Subsignal("rx_p", Pins("B6 B4")),
Subsignal("rx_n", Pins("A10")), Subsignal("rx_n", Pins("A6 A4")),
Subsignal("tx_p", Pins("B6")), Subsignal("tx_p", Pins("B2 D2")),
Subsignal("tx_n", Pins("A6")), Subsignal("tx_n", Pins("A2 D1")),
), ),
# SPIFlash. # SPIFlash.

2
litex_boards/targets/fairwaves_xtrx.py
View File

@ -79,7 +79,7 @@ class BaseSoC(SoCCore):
# PCIe ------------------------------------------------------------------------------------- # PCIe -------------------------------------------------------------------------------------
if with_pcie: if with_pcie:
self.submodules.pcie_phy = S7PCIEPHY(platform, platform.request("pcie_x1"), self.submodules.pcie_phy = S7PCIEPHY(platform, platform.request("pcie_x2"),
data_width = 64, data_width = 64,
bar0_size = 0x20000) bar0_size = 0x20000)
self.add_pcie(phy=self.pcie_phy, ndmas=1) self.add_pcie(phy=self.pcie_phy, ndmas=1)