fix cmdltncy, with_led
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parent
9e42183066
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@ -57,12 +57,12 @@ class _CRG(Module):
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# BaseSoC ------------------------------------------------------------------------------------------
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class BaseSoC(SoCCore):
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def __init__(self, sys_clk_freq=int(150e6), ddram_channel=0, with_pcie=False, **kwargs):
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def __init__(self, sys_clk_freq=int(150e6), ddram_channel=0, with_pcie=False, with_led=False, **kwargs):
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platform = alveo_u280.Platform()
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# SoCCore ----------------------------------------------------------------------------------
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SoCCore.__init__(self, platform, sys_clk_freq,
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ident = "LiteX SoC on Alveo U280",
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ident = "LiteX SoC on Alveo U280 (ES1)",
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ident_version = True,
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**kwargs)
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@ -73,8 +73,9 @@ class BaseSoC(SoCCore):
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if not self.integrated_main_ram_size:
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self.submodules.ddrphy = usddrphy.USPDDRPHY(platform.request("ddram", ddram_channel),
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memtype = "DDR4",
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cmd_latency = 1, # seems to work better with cmd_latency=1
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sys_clk_freq = sys_clk_freq,
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iodelay_clk_freq = 500e6,
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iodelay_clk_freq = 600e6,
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is_rdimm = True)
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self.add_sdram("sdram",
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phy = self.ddrphy,
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@ -94,9 +95,10 @@ class BaseSoC(SoCCore):
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self.add_pcie(phy=self.pcie_phy, ndmas=1)
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# Leds -------------------------------------------------------------------------------------
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self.submodules.leds = LedChaser(
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pads = platform.request_all("gpio_led"),
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sys_clk_freq = sys_clk_freq)
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if with_led:
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self.submodules.leds = LedChaser(
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pads = platform.request_all("gpio_led"),
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sys_clk_freq = sys_clk_freq)
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# Build --------------------------------------------------------------------------------------------
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@ -108,6 +110,7 @@ def main():
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parser.add_argument("--ddram-channel",default="0", help="DDRAM channel (default: 0)")
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parser.add_argument("--with-pcie", action="store_true", help="Enable PCIe support")
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parser.add_argument("--driver", action="store_true", help="Generate PCIe driver")
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parser.add_argument("--with-led", action="store_true", help="Enable LED Chaser")
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builder_args(parser)
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soc_core_args(parser)
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args = parser.parse_args()
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@ -116,6 +119,7 @@ def main():
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sys_clk_freq = int(float(args.sys_clk_freq)),
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ddram_channel = int(args.ddram_channel, 0),
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with_pcie = args.with_pcie,
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with_led = args.with_led,
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**soc_core_argdict(args)
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)
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builder = Builder(soc, **builder_argdict(args))
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