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Merge pull request #383 from sysmanalex/master 

Added Kintex-7 xc7k420t xc7k420tiffg901-2L named as u420t board
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enjoy-digital 2022-04-21 10:02:05 +02:00 committed by GitHub
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1
CONTRIBUTORS
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@ -85,3 +85,4 @@ Copyright (c) 2020 Vamsi K Vytla <vamsi.vytla@gmail.com>
Copyright (c) 2021 Vegard Storheil Eriksen <zyp@jvnv.net>
Copyright (c) 2020 YanekJ <yanekx@gmail.com>
Copyright (c) 2021 Yoshimasa Niwa <niw@niw.at>
Copyright (c) 2021 Alex Petrov <sysman@sysman.net>

1
README.md
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@ -204,6 +204,7 @@ Some of the suported boards, see yours? Give LiteX-Boards a try!
├── trenz_te0725
├── trenz_tec0117
├── tul_pynq_z2
├── u420t
├── xilinx_ac701
├── xilinx_alveo_u250
├── xilinx_alveo_u280

117
litex_boards/platforms/u420t.py Normal file
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@ -0,0 +1,117 @@
#
# This file is part of LiteX-Boards.
#
# Copyright (c) 2018-2019 Florent Kermarrec <florent@enjoy-digital.fr>
# SPDX-License-Identifier: BSD-2-Clause
# Kintex7-420T
# Part xc7k420tiffg901-2L v0.2 update
# ported by Alex Petrov aka sysman
from litex.build.generic_platform import *
from litex.build.xilinx import XilinxPlatform, VivadoProgrammer
from litex.build.openocd import OpenOCD
# IOs ----------------------------------------------------------------------------------------------
_io = [
# Clk / Rst
# u420t clk_y1 G27/ clk_y3 E25
("clk100", 0, Pins("G27"), IOStandard("LVCMOS33")),
#("sysclk", 0, Pins("E25"), IOStandard("LVCMOS33")),
#("clk100", 0,
# Subsignal("p", Pins("AB27"), IOStandard("DIFF_SSTL15")),
# Subsignal("n", Pins("AA27"), IOStandard("DIFF_SSTL15"))
#),
("cpu_reset", 0, Pins("W12"), IOStandard("LVCMOS33")),
# Leds board: D3-D10
("user_led", 0, Pins("AJ22"), IOStandard("LVCMOS33")),
("user_led", 1, Pins("AJ21"), IOStandard("LVCMOS33")),
("user_led", 2, Pins("AK21"), IOStandard("LVCMOS33")),
("user_led", 3, Pins("AK20"), IOStandard("LVCMOS33")),
("user_led", 4, Pins("AK19"), IOStandard("LVCMOS33")),
("user_led", 5, Pins("AJ19"), IOStandard("LVCMOS33")),
("user_led", 6, Pins("AK18"), IOStandard("LVCMOS33")),
("user_led", 7, Pins("AJ18"), IOStandard("LVCMOS33")),
# Buttons
("user_btn_k3", 0, Pins("AK15"), IOStandard("LVCMOS33")),
("user_btn_k2", 0, Pins("AK16"), IOStandard("LVCMOS33")),
# ("user_btnb", 0, Pins("AB11"), IOStandard("LVCMOS33")),
# http://www.wch-ic.com/products/CH340.html
# Serial CH340 , warning: wrong schema
("serial", 0,
Subsignal("tx", Pins("AK23")), ## U340 schem rx
Subsignal("rx", Pins("AJ23")), ## U340 schem tx
IOStandard("LVCMOS33")
),
# SPIFlash (Micron N25Q256A (32MB))
("spiflash", 0,
Subsignal("cs_n", Pins("V26"), IOStandard("LVCMOS33")),
#Subsignal("clk", Pins("G7"), IOStandard("LVCMOS33")),
Subsignal("mosi", Pins("R30"), IOStandard("LVCMOS33")),
Subsignal("miso", Pins("T30"), IOStandard("LVCMOS33")),
Subsignal("wp", Pins("R28"), IOStandard("LVCMOS33")),
Subsignal("hold", Pins("T28"), IOStandard("LVCMOS33"))
),
("spiflash4x", 0,
Subsignal("cs_n", Pins("V26"), IOStandard("LVCMOS33")),
#Subsignal("clk", Pins("")), # driven through JTAG H13 #T22 ?
Subsignal("dq", Pins("R30 T30 R28 T28"), IOStandard("LVCMOS33"))
),
]
# Connectors ---------------------------------------------------------------------------------------
# to add connector
_connectors = [
# main board connector, pins as marked
( "main", {
# usb- 1 2 usb+ not used U3 usb3320 don't use
# GND 3 4 GND
# QSPI_CS 5 6 QSPI_D1
# QSPI_D0 7 8 QSPI_CLK
9: "B29",
# 10: "Program_B" key3 reset button
11: "A28",
12: "B27",
13: "A27",
14: "A26",
15: "B25",
16: "A25",
17: "B24",
18: "B23",
19: "A23",
20: "B22",
21: "A22",
22: "A21",
23: "B20",
24: "A20",
# 25,26,27,28: GND
# 29,30,31,32: V12
})
]
# PMODS --------------------------------------------------------------------------------------------
# Platform -----------------------------------------------------------------------------------------
class Platform(XilinxPlatform):
default_clk_name = "clk100"
default_clk_period = 1e9/100e6
def __init__(self, toolchain="vivado"):
XilinxPlatform.__init__(self, "xc7k420tl-ffg901", _io, toolchain=toolchain)
# self.add_platform_command("")
# self.add_platform_command("set_property INTERNAL_VREF 0.900 [current_design]")
# self.add_platform_command("set_property INTERNAL_VREF 0.900 [get_iobanks 34]")
def create_programmer(self):
return OpenOCD("openocd_xc7_ft2232.cfg", "bscan_spi_xc7a420t.bit")
def do_finalize(self, fragment):
XilinxPlatform.do_finalize(self, fragment)
self.add_period_constraint(self.lookup_request("clk100", loose=True), 1e9/100e6)

120
litex_boards/targets/u420t.py Executable file
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#!/usr/bin/env python3
#
# This file is part of LiteX-Boards.
#
# Copyright (c) 2020-2021 Xuanyu Hu <xuanyu.hu@whu.edu.cn>
# SPDX-License-Identifier: BSD-2-Clause
# ported by Alex Petrov aka sysman
# Kintex7-420T aliexpress
# Part xc7k420tiffg901-2L v0.2
from migen import *
from litex_boards.platforms import u420t
from litex.soc.interconnect import wishbone
from litex.soc.cores.clock import *
from litex.soc.integration.soc import SoCRegion
from litex.soc.integration.soc_core import *
from litex.soc.integration.builder import *
from litex.soc.cores.led import LedChaser
# CRG ----------------------------------------------------------------------------------------------
class _CRG(Module):
def __init__(self, platform, sys_clk_freq):
self.rst = Signal()
self.clock_domains.cd_sys = ClockDomain()
self.clock_domains.cd_sys4x = ClockDomain(reset_less=True)
self.clock_domains.cd_idelay = ClockDomain()
# board is grade 2, but to fix halts use -1
self.submodules.pll = pll = S7MMCM(speedgrade=-2)
##self.submodules.pll = pll = S7MMCM(speedgrade=-1)
self.comb += pll.reset.eq(~platform.request("user_btn_k3") | self.rst)
pll.register_clkin(platform.request("clk100"), 100e6)
#workaround to bypass for clk100 error: No nets matched 'clk100'
#line:940 litex/litex/build/xilinx/vivado.py " [get_ports {clk}]", clk=clk)
## platform.add_platform_command("create_clock -name clk100 -period 10.0 [get_ports clk100]")
pll.create_clkout(self.cd_sys, sys_clk_freq)
pll.create_clkout(self.cd_sys4x, 4*sys_clk_freq)
pll.create_clkout(self.cd_idelay, 200e6)
platform.add_false_path_constraints(self.cd_sys.clk, pll.clkin) # Ignore sys_clk to pll.clkin path created by SoC's rst.
# platform.add_platform_command("set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk100]")
# Reduce programming time
#self.add_platform_command("set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]")
self.submodules.idelayctrl = S7IDELAYCTRL(self.cd_idelay)
# BaseSoC ------------------------------------------------------------------------------------------
class BaseSoC(SoCCore):
def __init__(self, sys_clk_freq=int(100e6), with_led_chaser=True, with_spi_flash=False, **kwargs):
platform = u420t.Platform()
# --- add more sram for riscv comfort
# xc7k420t BRAMs: 1670 (col length: RAMB18 160 RAMB36 80)
kwargs["integrated_rom_size"] = 0x8000 # 8kb
kwargs["integrated_sram_size"] = 0x10000 # 64kb
kwargs["integrated_main_ram_size"] = 0x40000 # 256kb ## change if needed
# SoCCore ----------------------------------_-----------------------------------------------
SoCCore.__init__(self, platform, sys_clk_freq,
ident = "LiteX SoC on u420t",
**kwargs)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform, sys_clk_freq)
# Video ------------------------------------------------------------------------------------
# no video
# no ram
# SPI Flash --------------------------------------------------------------------------------
if with_spi_flash:
from litespi.modules import N25Q256
from litespi.opcodes import SpiNorFlashOpCodes as Codes
self.add_spi_flash(mode="4x", module=W25Q256(Codes.READ_1_1_4))
# Leds -------------------------------------------------------------------------------------
if with_led_chaser:
self.submodules.leds = LedChaser(
pads = platform.request_all("user_led"),
sys_clk_freq = sys_clk_freq)
# Add ROM linker region --------------------------------------------------------------------
#self.bus.add_region("rom", SoCRegion(
# origin = self.bus.regions["spiflash"].origin + bios_flash_offset,
# size = 32*kB,
# linker = True)
#)
#self.cpu.set_reset_address(self.bus.regions["rom"].origin)
# Build --------------------------------------------------------------------------------------------
def main():
from litex.soc.integration.soc import LiteXSoCArgumentParser
parser = LiteXSoCArgumentParser(description="LiteX SoC on u420t")
target_group = parser.add_argument_group(title="Target options")
target_group.add_argument("--build", action="store_true", help="Build bitstream.")
target_group.add_argument("--load", action="store_true", help="Load bitstream.")
target_group.add_argument("--sys-clk-freq", default=100e6, help="System clock frequency.")
# sdopts = target_group.add_mutually_exclusive_group()
sdopts.add_argument("--with-spi-flash", action="store_true", help="Enable SPI-mode flash support.")
builder_args(parser)
soc_core_args(parser)
args = parser.parse_args()
soc = BaseSoC(
sys_clk_freq = int(float(args.sys_clk_freq)),
**soc_core_argdict(args)
)
# soc.platform.add_extension(u420t._sdcard_pmod_io)
builder = Builder(soc, **builder_argdict(args))
builder.build(run=args.build)
if args.load:
prog = soc.platform.create_programmer()
prog.load_bitstream(obuilder.get_bitstream_filename(mode="sram"))
if __name__ == "__main__":
main()