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platforms/mercury_xu5: replace ' with ".
This commit is contained in:
Florent Kermarrec
parent
dc1371108d
commit
8c535d15f2
1 changed files with 90 additions and 90 deletions
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@ -4,119 +4,119 @@ from litex.build.xilinx import XilinxPlatform, VivadoProgrammer
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# IOs ----------------------------------------------------------------------------------------------
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_io = [
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('clk100', 0,
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Subsignal('n', Pins('AD4'), IOStandard('DIFF_SSTL12_DCI')),
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Subsignal('p', Pins('AD5'), IOStandard('DIFF_SSTL12_DCI')),
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("clk100", 0,
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Subsignal("n", Pins("AD4"), IOStandard("DIFF_SSTL12_DCI")),
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Subsignal("p", Pins("AD5"), IOStandard("DIFF_SSTL12_DCI")),
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),
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('clk100_gtr', 0,
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Subsignal('p', Pins('C21'), IOStandard('DIFF_SSTL12')),
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Subsignal('n', Pins('C22'), IOStandard('DIFF_SSTL12')),
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("clk100_gtr", 0,
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Subsignal("p", Pins("C21"), IOStandard("DIFF_SSTL12")),
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Subsignal("n", Pins("C22"), IOStandard("DIFF_SSTL12")),
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),
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('clk27_gtr', 0,
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Subsignal('p', Pins('A21'), IOStandard('DIFF_SSTL12')),
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Subsignal('n', Pins('A22'), IOStandard('DIFF_SSTL12')),
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("clk27_gtr", 0,
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Subsignal("p", Pins("A21"), IOStandard("DIFF_SSTL12")),
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Subsignal("n", Pins("A22"), IOStandard("DIFF_SSTL12")),
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),
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('clk33', 0, Pins('AD4'), IOStandard('SSTL12')),
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("clk33", 0, Pins("AD4"), IOStandard("SSTL12")),
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('cpu_reset', 0, Pins('N19'), IOStandard('LVCMOS33')),
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("cpu_reset", 0, Pins("N19"), IOStandard("LVCMOS33")),
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('user_led', 0, Pins('H2'), IOStandard('LVCMOS18')),
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('user_led', 1, Pins('P9'), IOStandard('LVCMOS18')),
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('user_led', 2, Pins('K5'), IOStandard('LVCMOS18')),
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("user_led", 0, Pins("H2"), IOStandard("LVCMOS18")),
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("user_led", 1, Pins("P9"), IOStandard("LVCMOS18")),
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("user_led", 2, Pins("K5"), IOStandard("LVCMOS18")),
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('serial', 0,
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Subsignal('rx', Pins('AA10')), # Module connector A: A60 (Meccury PE1: "IO B" connector 32)
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Subsignal('tx', Pins('AA11')), # Module connector A: A58 (Meccury PE1: "IO B" connector 31)
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IOStandard('LVCMOS33'),
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("serial", 0,
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Subsignal("rx", Pins("AA10")), # Module connector A: A60 (Meccury PE1: "IO B" connector 32)
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Subsignal("tx", Pins("AA11")), # Module connector A: A58 (Meccury PE1: "IO B" connector 31)
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IOStandard("LVCMOS33"),
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),
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('ddram', 0, # TODO: remove Misc with default settings
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Subsignal('a', Pins(
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'AC4 AC3 AB4 AB3 AB2 AC2 AB1 AC1',
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'AB5 AG4 AH4 AG3 AH3 AE3'), IOStandard('SSTL12_DCI'),
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Misc('OUTPUT_IMPEDANCE=RDRV_40_40'),
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Misc('DATA_RATE=DDR'),
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("ddram", 0, # TODO: remove Misc with default settings
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Subsignal("a", Pins(
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"AC4 AC3 AB4 AB3 AB2 AC2 AB1 AC1",
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"AB5 AG4 AH4 AG3 AH3 AE3"), IOStandard("SSTL12_DCI"),
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Misc("OUTPUT_IMPEDANCE=RDRV_40_40"),
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Misc("DATA_RATE=DDR"),
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),
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Subsignal('we_n', Pins('AF3'), IOStandard('SSTL12_DCI'), # A14
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Misc('OUTPUT_IMPEDANCE=RDRV_40_40'),
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Misc('DATA_RATE=DDR'),
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Subsignal("we_n", Pins("AF3"), IOStandard("SSTL12_DCI"), # A14
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Misc("OUTPUT_IMPEDANCE=RDRV_40_40"),
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Misc("DATA_RATE=DDR"),
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),
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Subsignal('cas_n', Pins('AE2'), IOStandard('SSTL12_DCI'), # A15
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Misc('OUTPUT_IMPEDANCE=RDRV_40_40'),
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Misc('DATA_RATE=DDR'),
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Subsignal("cas_n", Pins("AE2"), IOStandard("SSTL12_DCI"), # A15
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Misc("OUTPUT_IMPEDANCE=RDRV_40_40"),
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Misc("DATA_RATE=DDR"),
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),
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Subsignal('ras_n', Pins('AF2'), IOStandard('SSTL12_DCI'), # A16
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Misc('OUTPUT_IMPEDANCE=RDRV_40_40'),
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Misc('DATA_RATE=DDR'),
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Subsignal("ras_n", Pins("AF2"), IOStandard("SSTL12_DCI"), # A16
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Misc("OUTPUT_IMPEDANCE=RDRV_40_40"),
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Misc("DATA_RATE=DDR"),
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),
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Subsignal('ba', Pins('AH1 AF1'), IOStandard('SSTL12_DCI'),
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Misc('OUTPUT_IMPEDANCE=RDRV_40_40'),
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Misc('DATA_RATE=DDR'),
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Subsignal("ba", Pins("AH1 AF1"), IOStandard("SSTL12_DCI"),
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Misc("OUTPUT_IMPEDANCE=RDRV_40_40"),
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Misc("DATA_RATE=DDR"),
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),
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# Subsignal('bg', Pins('AG1 AD9'), IOStandard('SSTL12_DCI'),
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Subsignal('bg', Pins('AG1'), IOStandard('SSTL12_DCI'),
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Misc('OUTPUT_IMPEDANCE=RDRV_40_40'),
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Misc('DATA_RATE=DDR'),
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# Subsignal("bg", Pins("AG1 AD9"), IOStandard("SSTL12_DCI"),
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Subsignal("bg", Pins("AG1"), IOStandard("SSTL12_DCI"),
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Misc("OUTPUT_IMPEDANCE=RDRV_40_40"),
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Misc("DATA_RATE=DDR"),
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),
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Subsignal('cs_n', Pins('AH9'), IOStandard('SSTL12_DCI'),
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Misc('OUTPUT_IMPEDANCE=RDRV_40_40'),
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Misc('DATA_RATE=SDR'),
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Subsignal("cs_n", Pins("AH9"), IOStandard("SSTL12_DCI"),
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Misc("OUTPUT_IMPEDANCE=RDRV_40_40"),
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Misc("DATA_RATE=SDR"),
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),
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Subsignal('act_n', Pins('AH2'), IOStandard('SSTL12_DCI'),
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Misc('OUTPUT_IMPEDANCE=RDRV_40_40'),
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Misc('DATA_RATE=DDR'),
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Subsignal("act_n", Pins("AH2"), IOStandard("SSTL12_DCI"),
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Misc("OUTPUT_IMPEDANCE=RDRV_40_40"),
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Misc("DATA_RATE=DDR"),
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),
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Subsignal('dm', Pins('AC9 AG9'), IOStandard('POD12_DCI'),
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Misc('OUTPUT_IMPEDANCE=RDRV_40_40'),
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# Misc('EQUALIZATION=EQ_LEVEL2'),
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Misc('DATA_RATE=DDR'),
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Subsignal("dm", Pins("AC9 AG9"), IOStandard("POD12_DCI"),
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Misc("OUTPUT_IMPEDANCE=RDRV_40_40"),
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# Misc("EQUALIZATION=EQ_LEVEL2"),
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Misc("DATA_RATE=DDR"),
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),
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Subsignal('dq', Pins(
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'AB6 AC6 AE9 AE8 AB8 AC8 AB7 AC7',
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'AE5 AF5 AF8 AG8 AH8 AH7 AF7 AF6'), IOStandard('POD12_DCI'),
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Misc('PRE_EMPHASIS=RDRV_240'),
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Misc('EQUALIZATION=EQ_LEVEL2'),
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Misc('OUTPUT_IMPEDANCE=RDRV_40_40'),
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Misc('DATA_RATE=DDR'),
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Misc('ODT=RTT_40'),
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Subsignal("dq", Pins(
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"AB6 AC6 AE9 AE8 AB8 AC8 AB7 AC7",
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"AE5 AF5 AF8 AG8 AH8 AH7 AF7 AF6"), IOStandard("POD12_DCI"),
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Misc("PRE_EMPHASIS=RDRV_240"),
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Misc("EQUALIZATION=EQ_LEVEL2"),
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Misc("OUTPUT_IMPEDANCE=RDRV_40_40"),
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Misc("DATA_RATE=DDR"),
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Misc("ODT=RTT_40"),
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),
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Subsignal('dqs_p', Pins('AD7 AG6'), IOStandard('DIFF_POD12_DCI'),
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Misc('PRE_EMPHASIS=RDRV_240'),
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Misc('EQUALIZATION=EQ_LEVEL2'),
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Misc('OUTPUT_IMPEDANCE=RDRV_40_40'),
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Misc('DATA_RATE=DDR'),
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Misc('ODT=RTT_40'),
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Subsignal("dqs_p", Pins("AD7 AG6"), IOStandard("DIFF_POD12_DCI"),
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Misc("PRE_EMPHASIS=RDRV_240"),
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Misc("EQUALIZATION=EQ_LEVEL2"),
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Misc("OUTPUT_IMPEDANCE=RDRV_40_40"),
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Misc("DATA_RATE=DDR"),
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Misc("ODT=RTT_40"),
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),
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Subsignal('dqs_n', Pins('AE7 AG5'), IOStandard('DIFF_POD12_DCI'),
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Misc('PRE_EMPHASIS=RDRV_240'),
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Misc('EQUALIZATION=EQ_LEVEL2'),
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Misc('OUTPUT_IMPEDANCE=RDRV_40_40'),
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Misc('DATA_RATE=DDR'),
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Misc('ODT=RTT_40'),
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Subsignal("dqs_n", Pins("AE7 AG5"), IOStandard("DIFF_POD12_DCI"),
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Misc("PRE_EMPHASIS=RDRV_240"),
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Misc("EQUALIZATION=EQ_LEVEL2"),
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Misc("OUTPUT_IMPEDANCE=RDRV_40_40"),
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Misc("DATA_RATE=DDR"),
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Misc("ODT=RTT_40"),
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),
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Subsignal('clk_p', Pins('AD2'), IOStandard('DIFF_SSTL12_DCI'),
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Misc('OUTPUT_IMPEDANCE=RDRV_40_40'),
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Misc('DATA_RATE=DDR'),
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Subsignal("clk_p", Pins("AD2"), IOStandard("DIFF_SSTL12_DCI"),
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Misc("OUTPUT_IMPEDANCE=RDRV_40_40"),
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Misc("DATA_RATE=DDR"),
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),
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Subsignal('clk_n', Pins('AD1'), IOStandard('DIFF_SSTL12_DCI'),
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Misc('OUTPUT_IMPEDANCE=RDRV_40_40'),
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Misc('DATA_RATE=DDR'),
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Subsignal("clk_n", Pins("AD1"), IOStandard("DIFF_SSTL12_DCI"),
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Misc("OUTPUT_IMPEDANCE=RDRV_40_40"),
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Misc("DATA_RATE=DDR"),
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),
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Subsignal('cke', Pins('AH6'), IOStandard('SSTL12_DCI'),
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Misc('OUTPUT_IMPEDANCE=RDRV_40_40'),
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Misc('DATA_RATE=DDR'),
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Subsignal("cke", Pins("AH6"), IOStandard("SSTL12_DCI"),
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Misc("OUTPUT_IMPEDANCE=RDRV_40_40"),
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Misc("DATA_RATE=DDR"),
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),
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Subsignal('odt', Pins('AE4'), IOStandard('SSTL12_DCI'),
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Misc('OUTPUT_IMPEDANCE=RDRV_40_40'),
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Misc('DATA_RATE=DDR'),
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Subsignal("odt", Pins("AE4"), IOStandard("SSTL12_DCI"),
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Misc("OUTPUT_IMPEDANCE=RDRV_40_40"),
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Misc("DATA_RATE=DDR"),
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),
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Subsignal('reset_n', Pins('G4'), IOStandard('LVCMOS18'),
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Misc('DRIVE=8'),
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Subsignal("reset_n", Pins("G4"), IOStandard("LVCMOS18"),
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Misc("DRIVE=8"),
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),
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Misc('SLEW=FAST'),
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Misc("SLEW=FAST"),
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),
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]
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@ -127,17 +127,17 @@ _connectors = []
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# Platform -----------------------------------------------------------------------------------------
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class Platform(XilinxPlatform):
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default_clk_name = 'clk100'
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default_clk_name = "clk100"
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default_clk_period = 1e9/100e6
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def __init__(self):
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XilinxPlatform.__init__(self, 'xczu2eg-sfvc784-1-i', _io, _connectors, toolchain='vivado')
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XilinxPlatform.__init__(self, "xczu2eg-sfvc784-1-i", _io, _connectors, toolchain="vivado")
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def create_programmer(self):
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return VivadoProgrammer()
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def do_finalize(self, fragment):
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XilinxPlatform.do_finalize(self, fragment)
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self.add_platform_command('set_property BITSTREAM.CONFIG.OVERTEMPSHUTDOWN ENABLE [current_design]')
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self.add_platform_command('set_property BITSTREAM.CONFIG.UNUSEDPIN PULLNONE [current_design]')
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self.add_platform_command('set_property INTERNAL_VREF 0.600 [get_iobanks 64]')
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self.add_platform_command("set_property BITSTREAM.CONFIG.OVERTEMPSHUTDOWN ENABLE [current_design]")
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self.add_platform_command("set_property BITSTREAM.CONFIG.UNUSEDPIN PULLNONE [current_design]")
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self.add_platform_command("set_property INTERNAL_VREF 0.600 [get_iobanks 64]")
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