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Update radiona_ulx4m_ld_v2.py

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Goran Mahovlic 2023-02-13 12:08:38 +01:00 committed by GitHub
parent 404fefaab1
commit 8c9ea15d0a
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litex_boards/targets/radiona_ulx4m_ld_v2.py
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@ -192,7 +192,7 @@ class BaseSoC(SoCCore):
# Build --------------------------------------------------------------------------------------------
def main():
parser = argparse.ArgumentParser(description="LiteX SoC on ULX4M-LD-V2")
parser = LiteXArgumentParser(platform=radiona_ulx4m_ld_v2.Platform, description="LiteX SoC on ULX4M-LD-V2")
parser.add_argument("--build", action="store_true", help="Build bitstream.")
parser.add_argument("--load", action="store_true", help="Load bitstream.")
parser.add_argument("--toolchain", default="trellis", help="FPGA toolchain (trellis or diamond).")