Merge pull request #37 from feliks-montez/master
Add Mimas A7 board support
This commit is contained in:
enjoy-digital
GitHub
commit
8d298951a8
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# This file is Copyright (c) 2015 Yann Sionneau <yann.sionneau@gmail.com>
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# This file is Copyright (c) 2015-2019 Florent Kermarrec <florent@enjoy-digital.fr>
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# This file is Copyright (c) 2020 Feliks Montez <feliks.montez@gmail.com>
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# License: BSD
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from litex.build.generic_platform import *
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from litex.build.xilinx import XilinxPlatform, VivadoProgrammer
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# IOs ----------------------------------------------------------------------------------------------
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_io = [
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("user_led", 0, Pins("K17"), IOStandard("LVCMOS33")),
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("user_led", 1, Pins("J17"), IOStandard("LVCMOS33")),
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("user_led", 2, Pins("L14"), IOStandard("LVCMOS33")),
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("user_led", 3, Pins("L15"), IOStandard("LVCMOS33")),
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("user_led", 4, Pins("L16"), IOStandard("LVCMOS33")),
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("user_led", 5, Pins("K16"), IOStandard("LVCMOS33")),
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("user_led", 6, Pins("M15"), IOStandard("LVCMOS33")),
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("user_led", 7, Pins("M16"), IOStandard("LVCMOS33")),
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("user_sw", 0, Pins("B21"), IOStandard("LVCMOS33")),
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("user_sw", 1, Pins("A21"), IOStandard("LVCMOS33")),
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("user_sw", 2, Pins("E22"), IOStandard("LVCMOS33")),
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("user_sw", 3, Pins("D22"), IOStandard("LVCMOS33")),
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("user_sw", 4, Pins("E21"), IOStandard("LVCMOS33")),
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("user_sw", 5, Pins("D21"), IOStandard("LVCMOS33")),
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("user_sw", 6, Pins("G21"), IOStandard("LVCMOS33")),
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("user_sw", 7, Pins("G22"), IOStandard("LVCMOS33")),
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("user_btn", 0, Pins("P20"), IOStandard("LVCMOS33")),
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("user_btn", 1, Pins("P19"), IOStandard("LVCMOS33")),
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("user_btn", 2, Pins("P17"), IOStandard("LVCMOS33")),
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("user_btn", 3, Pins("N17"), IOStandard("LVCMOS33")),
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("clk100", 0, Pins("H4"), IOStandard("LVCMOS33")),
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("cpu_reset", 0, Pins("M2"), IOStandard("LVCMOS33")),
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# Not usable unless EEPROM is reprogrammed to set Channel A of FT2232H to ASYNC Serial (UART) mode
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# ("serial", 0,
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# Subsignal("tx", Pins("Y22")),
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# Subsignal("rx", Pins("Y21")),
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# IOStandard("LVCMOS33")
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# ),
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# Not usable unless EEPROM is reprogrammed to set Channel A of FT2232H to ASYNC FIFO 245 mode
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# Host can interface with this as if it were UART--See issue https://github.com/enjoy-digital/litex/issues/231 for more info
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("usb_fifo", 0,
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Subsignal("data", Pins("Y22 Y21 AB22 AA21 AB21 AA20 AB20 AA18")),
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Subsignal("rxf_n", Pins("W21")),
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Subsignal("txe_n", Pins("V22")),
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Subsignal("rd_n", Pins("AA19")),
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Subsignal("wr_n", Pins("W22")),
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Subsignal("siwua", Pins("U21")),
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Subsignal("oe_n", Pins("T21")),
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IOStandard("LVCMOS33"), Drive(8), Misc("SLEW=FAST")
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),
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("spiflash4x", 0,
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Subsignal("cs_n", Pins("T19")),
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Subsignal("clk", Pins("L12")),
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Subsignal("dq", Pins("P22", "R22", "P21", "R21")),
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IOStandard("LVCMOS33")
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),
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("spiflash", 0,
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Subsignal("cs_n", Pins("T19")),
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Subsignal("clk", Pins("L12")),
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Subsignal("mosi", Pins("P22")),
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Subsignal("miso", Pins("R22")),
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Subsignal("wp", Pins("P21")),
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Subsignal("hold", Pins("R21")),
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IOStandard("LVCMOS33"),
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),
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# DDR3 MT41J128M16XX-125
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# freq: 400MHz, data width: 16
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("ddram", 0,
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Subsignal("a", Pins(
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"U6 T5 Y6 T6 V2 T4 Y2 R2",
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"Y1 R4 W5 W1 AA6 U2"),
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IOStandard("SSTL15")),
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Subsignal("ba", Pins("W6 U5 R6"), IOStandard("SSTL15")),
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Subsignal("ras_n", Pins("V5"), IOStandard("SSTL15")),
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Subsignal("cas_n", Pins("T1"), IOStandard("SSTL15")),
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Subsignal("we_n", Pins("R3"), IOStandard("SSTL15")),
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Subsignal("cs_n", Pins("T3"), IOStandard("SSTL15")),
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Subsignal("dm", Pins("Y7 AA1"), IOStandard("SSTL15")),
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Subsignal("dq", Pins(
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"Y8 AB6 W9 AA8 AB7 V7 AB8 W7",
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"V4 AB2 AA5 AB3 AB5 W4 AB1 AA4"),
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IOStandard("SSTL15")),
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Subsignal("dqs_p", Pins("V9 Y3"), IOStandard("DIFF_SSTL15")),
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Subsignal("dqs_n", Pins("V8 AA3"), IOStandard("DIFF_SSTL15")),
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Subsignal("clk_p", Pins("U3"), IOStandard("DIFF_SSTL15")),
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Subsignal("clk_n", Pins("V3"), IOStandard("DIFF_SSTL15")),
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Subsignal("cke", Pins("U1"), IOStandard("SSTL15")),
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Subsignal("odt", Pins("W2"), IOStandard("SSTL15")),
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Subsignal("reset_n", Pins("U7"), IOStandard("SSTL15")),
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Misc("SLEW=FAST"),
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),
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# Seven Seg display not yet mapped here
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# 24AA02E48T EEPROM
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("eeprom", 0,
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Subsignal("scl", Pins("N5")),
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Subsignal("sda", Pins("P6")),
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IOStandard("LVCMOS33")
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),
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# Micro SD not yet mapped here
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# FIXME not sure how to map ethernet. Is this RGMII?
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("eth_clocks", 0,
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Subsignal("tx", Pins("U20")),
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Subsignal("rx", Pins("W19")),
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IOStandard("LVCMOS33")
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),
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("eth", 0,
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Subsignal("rst_n", Pins("R14")),
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# Subsignal("int_n", Pins("Y14")), # usually RGMII has the int_n pin
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Subsignal("mdio", Pins("P16"), Misc("SLEW=FAST")),
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Subsignal("mdc", Pins("R19"), Misc("SLEW=FAST")),
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Subsignal("rx_ctl", Pins("Y19")),
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Subsignal("rx_data", Pins("AB18 W20 W17 V20")),
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Subsignal("tx_ctl", Pins("T20"), Misc("SLEW=FAST")),
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Subsignal("tx_data", Pins("V18 U18 V17 U17"), Misc("SLEW=FAST")),
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IOStandard("LVCMOS33")
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),
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("hdmi_in", 0,
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Subsignal("clk_p", Pins("K4"), IOStandard("TMDS_33")),
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Subsignal("clk_n", Pins("J4"), IOStandard("TMDS_33")),
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Subsignal("data0_p", Pins("K1"), IOStandard("TMDS_33")),
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Subsignal("data0_n", Pins("J1"), IOStandard("TMDS_33")),
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Subsignal("data1_p", Pins("M1"), IOStandard("TMDS_33")),
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Subsignal("data1_n", Pins("L1"), IOStandard("TMDS_33")),
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Subsignal("data2_p", Pins("P2"), IOStandard("TMDS_33")),
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Subsignal("data2_n", Pins("N2"), IOStandard("TMDS_33")),
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Subsignal("scl", Pins("J2"), IOStandard("LVCMOS33")),
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Subsignal("sda", Pins("H2"), IOStandard("LVCMOS33")),
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Subsignal("hpd_en", Pins("G2"), IOStandard("LVCMOS33")), # FIXME not sure if this is the hdmi_rx_hpa pin
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Subsignal("cec", Pins("K2"), IOStandard("LVCMOS33")),
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# Subsignal("txen", Pins("R3"), IOStandard("LVCMOS33")), # not sure if we need this
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),
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("hdmi_out", 0,
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Subsignal("clk_p", Pins("L3"), IOStandard("TMDS_33")),
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Subsignal("clk_n", Pins("K3"), IOStandard("TMDS_33")),
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Subsignal("data0_p", Pins("B1"), IOStandard("TMDS_33")),
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Subsignal("data0_n", Pins("A1"), IOStandard("TMDS_33")),
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Subsignal("data1_p", Pins("E1"), IOStandard("TMDS_33")),
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Subsignal("data1_n", Pins("D1"), IOStandard("TMDS_33")),
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Subsignal("data2_p", Pins("G1"), IOStandard("TMDS_33")),
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Subsignal("data2_n", Pins("F1"), IOStandard("TMDS_33")),
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Subsignal("scl", Pins("D2"), IOStandard("LVCMOS33")),
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Subsignal("sda", Pins("C2"), IOStandard("LVCMOS33")),
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Subsignal("cec", Pins("E2"), IOStandard("LVCMOS33")),
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Subsignal("hdp", Pins("B2"), IOStandard("LVCMOS25")), # FIXME should this be hpd?
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),
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# Mini display ports not yet mapped here
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]
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# Connectors ---------------------------------------------------------------------------------------
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_connectors = [
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("P12", "J20 J21 K21 K22 H20 G20 J19 H19 J22 H22 K18 K19 L19 L20 M21 N22 N20 M20 M18 L18 N18 N19 H17 H18 G17 G18 G15 G16 J15 H15 K13 K14 M13 K14 M13 L13 J14 H14 H13 G13"),
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("P13", "F19 F20 E19 D19 D20 C20 C22 B22 F18 E18 C18 C19 D17 C17 B20 A20 B17 B18 A18 A19 E16 D16 B15 B16 A15 A16 C14 C15 A13 A14 C13 B13 D14 D15 E13 E14 F13 F14 F16 E17")
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]
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# Platform -----------------------------------------------------------------------------------------
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class Platform(XilinxPlatform):
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default_clk_name = "clk100"
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default_clk_period = 1e9/100e6
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def __init__(self, variant="50t"):
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device = {
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"50t": "xc7a50tfgg484-1"
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}[variant]
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XilinxPlatform.__init__(self, device, _io, _connectors, toolchain="vivado")
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self.toolchain.bitstream_commands = \
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["set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]"]
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self.toolchain.additional_commands = \
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["write_cfgmem -force -format bin -interface spix4 -size 16 "
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"-loadbit \"up 0x0 {build_name}.bit\" -file {build_name}.bin"]
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self.add_platform_command("set_property INTERNAL_VREF 0.675 [get_iobanks 34]")
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def create_programmer(self):
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return VivadoProgrammer(flash_part="n25q128-3.3v-spi-x1_x2_x4")
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@ -0,0 +1,121 @@
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#!/usr/bin/env python3
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# This file is Copyright (c) 2015-2019 Florent Kermarrec <florent@enjoy-digital.fr>
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# This file is Copyright (c) 2020 Feliks Montez <feliks.montez@gmail.com>
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# License: BSD
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import argparse
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from migen import *
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from litex_boards.platforms import mimas_a7
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from litex.build.xilinx.vivado import vivado_build_args, vivado_build_argdict
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from litex.soc.cores.clock import *
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from litex.soc.integration.soc_sdram import *
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from litex.soc.integration.builder import *
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from litedram.modules import MT41J128M16
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from litedram.phy import s7ddrphy
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from liteeth.phy.s7rgmii import LiteEthPHYRGMII
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from liteeth.mac import LiteEthMAC
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# CRG ----------------------------------------------------------------------------------------------
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class _CRG(Module):
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def __init__(self, platform, sys_clk_freq):
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self.clock_domains.cd_sys = ClockDomain()
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self.clock_domains.cd_sys4x = ClockDomain(reset_less=True)
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self.clock_domains.cd_sys4x_dqs = ClockDomain(reset_less=True)
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self.clock_domains.cd_clk200 = ClockDomain()
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# # #
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self.submodules.pll = pll = S7PLL(speedgrade=-1)
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self.comb += pll.reset.eq(platform.request("cpu_reset"))
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pll.register_clkin(platform.request("clk100"), 100e6)
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pll.create_clkout(self.cd_sys, sys_clk_freq)
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pll.create_clkout(self.cd_sys4x, 4*sys_clk_freq)
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pll.create_clkout(self.cd_sys4x_dqs, 4*sys_clk_freq, phase=90)
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pll.create_clkout(self.cd_clk200, 200e6)
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self.submodules.idelayctrl = S7IDELAYCTRL(self.cd_clk200)
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# BaseSoC ------------------------------------------------------------------------------------------
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class BaseSoC(SoCSDRAM):
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def __init__(self, sys_clk_freq=int(100e6), integrated_rom_size=0x8000, uart_name="usb_fifo", **kwargs):
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platform = mimas_a7.Platform()
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# SoCSDRAM ---------------------------------------------------------------------------------
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SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq,
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integrated_rom_size=integrated_rom_size,
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integrated_sram_size=0x8000,
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uart_name=uart_name,
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**kwargs)
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# CRG --------------------------------------------------------------------------------------
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self.submodules.crg = _CRG(platform, sys_clk_freq)
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# DDR3 SDRAM -------------------------------------------------------------------------------
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if not self.integrated_main_ram_size:
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self.submodules.ddrphy = s7ddrphy.A7DDRPHY(platform.request("ddram"),
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memtype = "DDR3",
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nphases = 4,
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sys_clk_freq = sys_clk_freq)
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self.add_csr("ddrphy")
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sdram_module = MT41J128M16(sys_clk_freq, "1:4")
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self.register_sdram(self.ddrphy,
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geom_settings = sdram_module.geom_settings,
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timing_settings = sdram_module.timing_settings)
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# EthernetSoC --------------------------------------------------------------------------------------
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class EthernetSoC(BaseSoC):
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mem_map = {
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"ethmac": 0xb0000000,
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}
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mem_map.update(BaseSoC.mem_map)
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def __init__(self, **kwargs):
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BaseSoC.__init__(self, integrated_rom_size=0x10000, **kwargs)
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self.submodules.ethphy = LiteEthPHYRGMII(self.platform.request("eth_clocks"),
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self.platform.request("eth"))
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self.add_csr("ethphy")
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self.submodules.ethmac = LiteEthMAC(phy=self.ethphy, dw=32,
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interface="wishbone", endianness=self.cpu.endianness)
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self.add_wb_slave(self.mem_map["ethmac"], self.ethmac.bus, 0x2000)
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self.add_memory_region("ethmac", self.mem_map["ethmac"], 0x2000, type="io")
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self.add_csr("ethmac")
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self.add_interrupt("ethmac")
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self.platform.add_period_constraint(self.ethphy.crg.cd_eth_rx.clk, 1e9/12.5e6)
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self.platform.add_period_constraint(self.ethphy.crg.cd_eth_tx.clk, 1e9/12.5e6)
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self.platform.add_false_path_constraints(
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self.crg.cd_sys.clk,
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self.ethphy.crg.cd_eth_rx.clk,
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self.ethphy.crg.cd_eth_tx.clk)
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# Build --------------------------------------------------------------------------------------------
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def main():
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parser = argparse.ArgumentParser(description="LiteX SoC on Mimas A7")
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builder_args(parser)
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soc_sdram_args(parser)
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vivado_build_args(parser)
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parser.add_argument("--with-ethernet", action="store_true",
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help="enable Ethernet support")
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args = parser.parse_args()
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cls = EthernetSoC if args.with_ethernet else BaseSoC
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soc = cls(**soc_sdram_argdict(args))
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builder = Builder(soc, **builder_argdict(args))
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builder.build(**vivado_build_argdict(args))
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||||||
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||||||
|
if __name__ == "__main__":
|
||||||
|
main()
|
||||||
Loading…
Reference in New Issue