Merge pull request #546 from hansfbaier/master
Add AliExpress Kintex XC7K70T board
This commit is contained in:
enjoy-digital
GitHub
commit
8f43cfe18c
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#
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# This file is part of LiteX-Boards.
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#
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# Copyright (c) 2023 Hans Baier <hansfbaier@gmail.com>
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# SPDX-License-Identifier: BSD-2-Clause
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from litex.build.generic_platform import *
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from litex.build.xilinx import Xilinx7SeriesPlatform
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from litex.build.openocd import OpenOCD
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# This board is available here:
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# https://www.aliexpress.com/item/1005005572549665.html
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# IOs ----------------------------------------------------------------------------------------------
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_io = [
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# Clk / Rst
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("clk50", 0, Pins("E11"), IOStandard("LVCMOS33")),
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("sma_global_clock", 0, Pins("C12"), IOStandard("LVCMOS33")),
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("sma_global_clock", 1, Pins("C11"), IOStandard("LVCMOS33")),
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# Leds
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("user_led", 0, Pins("AD9"), IOStandard("LVCMOS18")),
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("user_led", 1, Pins("AD8"), IOStandard("LVCMOS18")),
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("user_led", 2, Pins("AC9"), IOStandard("LVCMOS18")),
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("user_led", 3, Pins("AC8"), IOStandard("LVCMOS18")),
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# Buttons
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("user_btn_n", 0, Pins("AF7"), IOStandard("LVCMOS18")),
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("user_btn_n", 1, Pins("AF8"), IOStandard("LVCMOS18")),
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("user_btn_n", 2, Pins("AE8"), IOStandard("LVCMOS18")),
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("user_btn_n", 3, Pins("AF9"), IOStandard("LVCMOS18")),
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# Serial
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("serial", 0,
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Subsignal("tx", Pins("HR_IO:0")),
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Subsignal("rx", Pins("HR_IO:1")),
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IOStandard("LVCMOS33")
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),
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# SDRAM
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("sdram_clock", 0, Pins("P23"), IOStandard("LVCMOS33"), Misc("SLEW=FAST")),
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("sdram", 0,
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Subsignal("a", Pins("L25 L24 K23 M26 G25 F24 H26 F23 E23 J26 M25 G24")),
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Subsignal("dq", Pins("T23 T25 T24 R25 R23 R26 P24 P25 F25 H24 E26 H23 E25 J24 D26 J23")),
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Subsignal("ba", Pins("K25 M24")),
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Subsignal("dm", Pins("N23 G26")),
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Subsignal("ras_n", Pins("N24")),
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Subsignal("cas_n", Pins("K26")),
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Subsignal("we_n", Pins("P26")),
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Subsignal("cs_n", Pins("N26")),
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Subsignal("cke", Pins("J25")),
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IOStandard("LVCMOS33"),
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Misc("SLEW = FAST")
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),
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("spiflash4x", 0, # clock needs to be accessed through STARTUPE2
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Subsignal("cs_n", Pins("C23")),
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Subsignal("dq", Pins("B24 A25 B22 A22")),
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IOStandard("LVCMOS33")
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),
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("spiflash8x", 0,
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Subsignal("clk", Pins("A14")),
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Subsignal("cs_n", Pins("B11")),
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Subsignal("dq", Pins("A13 A10 B10 B14 A15 B12 A12 B15")),
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IOStandard("LVCMOS33")
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),
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# RGMII Ethernet
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("eth_clocks", 0,
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Subsignal("tx", Pins("AF13"), IOStandard("LVCMOS18")),
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Subsignal("rx", Pins("AB11"), IOStandard("LVCMOS18"))
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),
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("eth", 0,
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# Subsignal("rst_n", Pins("")),
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Subsignal("mdio", Pins("AD13")),
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Subsignal("mdc", Pins("AC13")),
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Subsignal("rx_ctl", Pins("AF10")),
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Subsignal("rx_data", Pins("AE10 AE11 AF12 AE12")),
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Subsignal("tx_ctl", Pins("AE13")),
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Subsignal("tx_data", Pins("AD10 AD11 AC11 AC12")),
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IOStandard("LVCMOS18")
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),
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# camera connector I2C, has pull up resistors
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("i2c", 0,
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Subsignal("scl", Pins("C13")),
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Subsignal("sda", Pins("C16")),
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IOStandard("LVCMOS33"),
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),
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("camera", 0,
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Subsignal("d", Pins("C17 B16 A17 B17 A18 D16 C18 D13")),
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Subsignal("vsync", Pins("C14")),
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Subsignal("xclk", Pins("C19")),
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Subsignal("pclk", Pins("E18")),
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Subsignal("pwdn", Pins("D11")),
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Subsignal("reset", Pins("D15")),
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Subsignal("href", Pins("D14")),
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IOStandard("LVCMOS33"),
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),
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# HDMI out
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("hdmi_out", 0,
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Subsignal("clk_p", Pins("E10"), IOStandard("TMDS_33")),
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Subsignal("clk_n", Pins("D10"), IOStandard("TMDS_33")),
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Subsignal("data0_p", Pins("D9"), IOStandard("TMDS_33")),
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Subsignal("data0_n", Pins("D8"), IOStandard("TMDS_33")),
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Subsignal("data1_p", Pins("C9"), IOStandard("TMDS_33")),
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Subsignal("data1_n", Pins("B9"), IOStandard("TMDS_33")),
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Subsignal("data2_p", Pins("A9"), IOStandard("TMDS_33")),
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Subsignal("data2_n", Pins("A8"), IOStandard("TMDS_33")),
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),
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# PCIe
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("pcie_x1", 0,
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Subsignal("rst_n", Pins("F8"), IOStandard("LVCMOS33")),
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Subsignal("clk_p", Pins("F5")),
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Subsignal("clk_n", Pins("F6")),
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Subsignal("rx_p", Pins("B6")),
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Subsignal("rx_n", Pins("B5")),
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Subsignal("tx_p", Pins("A4")),
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Subsignal("tx_n", Pins("A3"))
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),
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("pcie_x2", 0,
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Subsignal("rst_n", Pins("F8"), IOStandard("LVCMOS33")),
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Subsignal("clk_p", Pins("F5")),
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Subsignal("clk_n", Pins("F6")),
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Subsignal("rx_p", Pins("B6 C4")),
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Subsignal("rx_n", Pins("B5 C3")),
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Subsignal("tx_p", Pins("A4 B2")),
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Subsignal("tx_n", Pins("A3 B1"))
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),
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("pcie_x4", 0,
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Subsignal("rst_n", Pins("F8"), IOStandard("LVCMOS33")),
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Subsignal("clk_p", Pins("F5")),
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Subsignal("clk_n", Pins("F6")),
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Subsignal("rx_p", Pins("B6 C4 E4 G4")),
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Subsignal("rx_n", Pins("B5 C3 E3 G3")),
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Subsignal("tx_p", Pins("A4 B2 D2 F2")),
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Subsignal("tx_n", Pins("A3 B1 D1 F1"))
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),
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]
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# Connectors ---------------------------------------------------------------------------------------
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_connectors = [
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# 1.8V
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("HP_IO", {
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"0_P" : "AE6",
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"0_N" : "AE5",
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"1_P" : "AD6",
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"1_N" : "AD5",
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"2_P" : "AF5",
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"2_N" : "AF4",
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"3_P" : "AD4",
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"3_N" : "AD3",
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"4_P" : "AF3",
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"4_N" : "AF2",
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"5_P" : "AE3",
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"5_N" : "AE2",
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"6_P" : "AB2",
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"6_N" : "AC2",
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"7_P" : "V2",
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"7_N" : "V1",
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"8_P" : "AA3",
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"8_N" : "AA2",
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"9_P" : "AB1",
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"9_N" : "AC1",
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"10_P" : "W1",
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"10_N" : "Y1",
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"11_P" : "AD1",
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"11_N" : "AE1",
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}),
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# 3.3V
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("HR_IO", {
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0 : "D19",
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1 : "D18",
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2 : "C21",
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3 : "D20",
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4 : "C22",
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5 : "D21",
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6 : "C24",
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7 : "D23",
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8 : "D24",
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9 : "A19",
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10 : "B19",
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11 : "A20",
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12 : "B20",
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13 : "B21",
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14 : "A23",
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15 : "A24",
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16 : "B25",
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17 : "B26",
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18 : "C26",
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19 : "D25",
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}),
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# 3.3V
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("CAM", {
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3 : "C14",
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4 : "C13", # has pull up resistor
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5 : "D14",
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6 : "C16", # has pull up resistor
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7 : "D15",
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8 : "C17",
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9 : "B16",
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10 : "A17",
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11 : "B17",
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12 : "A18",
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13 : "D16",
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14 : "C18",
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15 : "D13",
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16 : "E18",
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17 : "C19",
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18 : "D11",
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})
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]
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# Platform -----------------------------------------------------------------------------------------
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class Platform(Xilinx7SeriesPlatform):
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default_clk_name = "clk50"
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default_clk_period = 1e9/50e6
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def __init__(self):
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Xilinx7SeriesPlatform.__init__(self, "xc7k70t-fbg676-1", _io, _connectors, toolchain="vivado")
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self.add_platform_command("""
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set_property CFGBVS VCCO [current_design]
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set_property CONFIG_VOLTAGE 3.3 [current_design]
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set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
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""")
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self.toolchain.bitstream_commands = ["set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]"]
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self.toolchain.additional_commands = ["write_cfgmem -force -format bin -interface spix4 -size 16 -loadbit \"up 0x0 {build_name}.bit\" -file {build_name}.bin"]
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def create_programmer(self):
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return OpenOCD("openocd_xc7_ft4232.cfg", "bscan_spi_xc7k70t.bit")
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def do_finalize(self, fragment):
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Xilinx7SeriesPlatform.do_finalize(self, fragment)
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self.add_period_constraint(self.lookup_request("eth_clocks:rx", 0, loose=True), 1e9/125e6)
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self.add_period_constraint(self.lookup_request("eth_clocks:tx", 0, loose=True), 1e9/125e6)
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@ -0,0 +1,166 @@
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#!/usr/bin/env python3
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#
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# This file is part of LiteX-Boards.
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#
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# Copyright (c) 2021 Nathaniel Lewis <github@nrlewis.dev>
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# Copyright (c) 2023 Hans Baier <hansfbaier@gmail.com>
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# SPDX-License-Identifier: BSD-2-Clause
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from migen import *
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from litex.gen import *
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from litex.build.io import DDROutput
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from litex_boards.platforms import aliexpress_xc7k70t
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from litex.soc.interconnect.csr import *
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from litex.soc.integration.soc_core import *
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from litex.soc.integration.builder import *
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from litex.soc.cores.clock import *
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from litex.soc.cores.video import VideoS7HDMIPHY
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from litex.soc.cores.led import LedChaser
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from litedram.modules import W9812G6JB, SDRModule
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from litedram.phy import GENSDRPHY, HalfRateGENSDRPHY
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# CRG ----------------------------------------------------------------------------------------------
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class CRG(LiteXModule):
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def __init__(self, platform, sys_clk_freq, sdram_rate="1:1"):
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self.rst = Signal()
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self.cd_sys = ClockDomain()
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self.cd_hdmi = ClockDomain()
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self.cd_hdmi5x = ClockDomain()
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if sdram_rate == "1:2":
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self.cd_sys2x = ClockDomain()
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self.cd_sys2x_ps = ClockDomain()
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else:
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self.cd_sys_ps = ClockDomain()
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# Clk/Rst
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clk50 = platform.request("clk50")
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# PLL
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self.pll = pll = S7PLL()
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self.comb += pll.reset.eq(self.rst)
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pll.register_clkin(clk50, 50e6)
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pll.create_clkout(self.cd_sys, sys_clk_freq)
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pll.create_clkout(self.cd_hdmi, 25e6, margin=0)
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pll.create_clkout(self.cd_hdmi5x, 125e6, margin=0)
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if sdram_rate == "1:2":
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pll.create_clkout(self.cd_sys2x, 2*sys_clk_freq)
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pll.create_clkout(self.cd_sys2x_ps, 2*sys_clk_freq, phase=90)
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else:
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pll.create_clkout(self.cd_sys_ps, sys_clk_freq, phase=90)
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# BaseSoC -----------------------------------------------------------------------------------------
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class BaseSoC(SoCCore):
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def __init__(self, sys_clk_freq=100e6, sdram_rate="1:1",
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with_hdmi = False,
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with_ethernet = False,
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with_jtagbone = False,
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with_pcie = False,
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with_sdram = True,
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with_led_chaser = True,
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with_video_terminal = False,
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with_video_framebuffer = False,
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with_video_colorbars = False,
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**kwargs):
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platform = aliexpress_xc7k70t.Platform()
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# CRG --------------------------------------------------------------------------------------
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self.crg = CRG(platform, sys_clk_freq, sdram_rate)
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# SoCCore ----------------------------------------------------------------------------------
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SoCCore.__init__(self, platform, sys_clk_freq, ident="LiteX SoC on Alchitry Mojo", **kwargs)
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# Add SDRAM if a shield with RAM has been added
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if not self.integrated_main_ram_size:
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sdram_clk = ClockSignal("sys2x_ps" if sdram_rate == "1:2" else "sys_ps")
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self.crg.specials += DDROutput(1, 0, platform.request("sdram_clock"), sdram_clk)
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sdrphy_cls = HalfRateGENSDRPHY if sdram_rate == "1:2" else GENSDRPHY
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self.sdrphy = sdrphy_cls(platform.request("sdram"), sys_clk_freq)
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self.add_sdram("sdram",
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phy = self.sdrphy,
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module = W9812G6JB(sys_clk_freq, sdram_rate),
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l2_cache_size = kwargs.get("l2_size", 1024)
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)
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# HDMI Options -----------------------------------------------------------------------------
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if with_hdmi and (with_video_colorbars or with_video_framebuffer or with_video_terminal):
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self.videophy = VideoS7HDMIPHY(platform.request("hdmi_out"), clock_domain="hdmi")
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if with_video_colorbars:
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self.add_video_colorbars(phy=self.videophy, timings="640x480@60Hz", clock_domain="hdmi")
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if with_video_terminal:
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self.add_video_terminal(phy=self.videophy, timings="640x480@60Hz", clock_domain="hdmi")
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if with_video_framebuffer:
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self.add_video_framebuffer(phy=self.videophy, timings="640x480@60Hz", clock_domain="hdmi")
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# Jtagbone ---------------------------------------------------------------------------------
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if with_jtagbone:
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self.add_jtagbone()
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# Ethernet / Etherbone ---------------------------------------------------------------------
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if with_ethernet:
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self.ethphy = LiteEthPHYRGMII(
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clock_pads = self.platform.request("eth_clocks", 0),
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pads = self.platform.request("eth", 0),
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tx_delay = 1.417e-9,
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rx_delay = 1.417e-9,
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)
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self.add_ethernet(phy=self.ethphy)
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# PCIe -------------------------------------------------------------------------------------
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if with_pcie:
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self.pcie_phy = S7PCIEPHY(platform, platform.request("pcie_x4"),
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data_width = 128,
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bar0_size = 0x20000)
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self.add_pcie(phy=self.pcie_phy, ndmas=1)
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# Leds -------------------------------------------------------------------------------------
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if with_led_chaser:
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self.leds = LedChaser(
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pads = platform.request_all("user_led"),
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sys_clk_freq = sys_clk_freq)
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# Build --------------------------------------------------------------------------------------------
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def main():
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from litex.build.parser import LiteXArgumentParser
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parser = LiteXArgumentParser(platform=aliexpress_xc7k70t.Platform, description="LiteX SoC on AliExpress XC7K70T PCIe board.")
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parser.add_target_argument("--sys-clk-freq", default=90e6, type=float, help="System clock frequency.")
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parser.add_target_argument("--sdram-rate", default="1:1", help="SDRAM Rate: (1:1 Full Rate or 1:2 Half Rate).")
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parser.add_argument("--with-ethernet", action="store_true", help="Enable ethernet")
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parser.add_argument("--with-jtagbone", action="store_true", help="Enable JTAGbone")
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parser.add_argument("--with-pcie", action="store_true", help="Enable PCIe")
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parser.add_argument("--with-hdmi", action="store_true", help="Enable HDMI")
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viopts = parser.target_group.add_mutually_exclusive_group()
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viopts.add_argument("--with-video-terminal", action="store_true", help="Enable Video Terminal (HDMI).")
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viopts.add_argument("--with-video-framebuffer", action="store_true", help="Enable Video Framebuffer (HDMI).")
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viopts.add_argument("--with-video-colorbars", action="store_true", help="Enable Video Colorbars (HDMI).")
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args = parser.parse_args()
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||||
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||||
# Note: baudrate is fixed because regardless of USB->TTL baud, the AVR <-> FPGA baudrate is
|
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# set to a fixed rate of 500 kilobaud.
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||||
soc = BaseSoC(
|
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sys_clk_freq = args.sys_clk_freq,
|
||||
sdram_rate = args.sdram_rate,
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||||
with_ethernet = args.with_ethernet,
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||||
with_pcie = args.with_pcie,
|
||||
with_jtagbone = args.with_jtagbone,
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||||
with_hdmi = args.with_hdmi,
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with_video_terminal = args.with_video_terminal,
|
||||
with_video_framebuffer = args.with_video_framebuffer,
|
||||
with_video_colorbars = args.with_video_colorbars,
|
||||
**parser.soc_argdict
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||||
)
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||||
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||||
builder = Builder(soc, **parser.builder_argdict)
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||||
if args.build:
|
||||
builder.build(**parser.toolchain_argdict)
|
||||
|
||||
if __name__ == "__main__":
|
||||
main()
|
||||
Loading…
Reference in New Issue