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targets/versa_ecp5: Fix LiteEthPHYRMGII tx/rx delays (need to be updated due to a bug fix in the ECP5RGMII PHY).

This commit is contained in:
Florent Kermarrec 2021-03-08 17:39:13 +01:00
parent 9cdcb8cb43
commit 8fb80053f7
1 changed files with 4 additions and 2 deletions
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4
litex_boards/targets/versa_ecp5.py
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@ -117,7 +117,9 @@ class BaseSoC(SoCCore):
if with_ethernet or with_etherbone: if with_ethernet or with_etherbone:
self.submodules.ethphy = LiteEthPHYRGMII( self.submodules.ethphy = LiteEthPHYRGMII(
clock_pads = self.platform.request("eth_clocks", eth_phy), clock_pads = self.platform.request("eth_clocks", eth_phy),
pads = self.platform.request("eth", eth_phy)) pads = self.platform.request("eth", eth_phy),
tx_delay = 0e-9,
rx_delay = 0e-9)
self.add_csr("ethphy") self.add_csr("ethphy")
if with_ethernet: if with_ethernet:
self.add_ethernet(phy=self.ethphy) self.add_ethernet(phy=self.ethphy)