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Merge pull request #291 from sergachev/master 

sqrl_acorn: add vivado programmer option, fix warnings
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enjoy-digital 2021-11-07 22:14:11 +01:00 committed by GitHub
parent 3dbad2ee06 099d947a49
commit 91d0cd50ea
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1 changed files with 10 additions and 4 deletions
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12
litex_boards/platforms/sqrl_acorn.py
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@ -12,7 +12,7 @@
# RHSResearchLLC that are documented at: https://github.com/RHSResearchLLC/NiteFury-and-LiteFury.
from litex.build.generic_platform import *
from litex.build.xilinx import XilinxPlatform
from litex.build.xilinx import XilinxPlatform, VivadoProgrammer
from litex.build.openocd import OpenOCD
# IOs ----------------------------------------------------------------------------------------------
@ -124,14 +124,20 @@ class Platform(XilinxPlatform):
self.toolchain.bitstream_commands = [
"set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]",
"set_property BITSTREAM.CONFIG.CONFIGRATE 16 [current_design]",
"set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]"
"set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]",
"set_property CFGBVS VCCO [current_design]",
"set_property CONFIG_VOLTAGE 3.3 [current_design]",
]
self.toolchain.additional_commands = \
["write_cfgmem -force -format bin -interface spix4 -size 16 "
"-loadbit \"up 0x0 {build_name}.bit\" -file {build_name}.bin"]
def create_programmer(self):
def create_programmer(self, name='openocd'):
if name == 'openocd':
return OpenOCD("openocd_xc7_ft232.cfg", "bscan_spi_xc7a200t.bit")
elif name == 'vivado':
# TODO: some board versions may have s25fl128s
return VivadoProgrammer(flash_part='s25fl256sxxxxxx0-spi-x1_x2_x4')
def do_finalize(self, fragment):
XilinxPlatform.do_finalize(self, fragment)