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sipeed_tang_nano_4k: Switch to LiteX's UART and expose hyperram parameter.

This commit is contained in:
Florent Kermarrec 2024-01-11 13:54:44 +01:00
parent 688a020f35
commit 926d54cb41
2 changed files with 2 additions and 3 deletions
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litex_boards/targets/build_working/sipeed_tang_nano_4k/software/liblitespi/spiflash.o Normal file
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5
litex_boards/targets/sipeed_tang_nano_4k.py
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@ -74,7 +74,6 @@ class BaseSoC(SoCCore):
# SoCCore ----------------------------------------------------------------------------------
if "cpu_type" in kwargs and kwargs["cpu_type"] == "gowin_emcu":
kwargs["with_uart"] = False # CPU has own UART
kwargs["integrated_sram_size"] = 0 # SRAM is directly attached to CPU
kwargs["integrated_rom_size"] = 0 # boot flash directly attached to CPU
else:
@ -87,8 +86,6 @@ class BaseSoC(SoCCore):
# Gowin EMCU -------------------------------------------------------------------------------
if self.cpu_type == "gowin_emcu":
# Use EMCU's UART.
self.cpu.connect_uart(platform.request("serial"))
# Use EMCU's SRAM.
self.bus.add_region("sram", SoCRegion(
origin = self.cpu.mem_map["sram"],
@ -152,11 +149,13 @@ def main():
parser = LiteXArgumentParser(platform=sipeed_tang_nano_4k.Platform, description="LiteX SoC on Tang Nano 4K.")
parser.add_target_argument("--flash", action="store_true", help="Flash Bitstream and BIOS.")
parser.add_target_argument("--sys-clk-freq", default=27e6, type=float, help="System clock frequency.")
parser.add_target_argument("--with-hyperram", action="store_true", help="Enable HyperRAM.")
parser.add_target_argument("--with-video-terminal", action="store_true", help="Enable Video Terminal (HDMI).")
args = parser.parse_args()
soc = BaseSoC(
sys_clk_freq = args.sys_clk_freq,
with_hyperram = args.with_hyperram,
with_video_terminal = args.with_video_terminal,
**parser.soc_argdict
)