fixed review remarks; added zynq7000 as a submodule for using the ps as a slave
This commit is contained in:
mkuhn99
parent
c489347a51
commit
926ed21f0b
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@ -5,7 +5,7 @@
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# SPDX-License-Identifier: BSD-2-Clause
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from litex.build.generic_platform import *
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from litex.build.xilinx import Xilinx7SeriesPlatform, VivadoProgrammer, XilinxPlatform
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from litex.build.xilinx import Xilinx7SeriesPlatform, VivadoProgrammer
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# IOs ----------------------------------------------------------------------------------------------
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@ -80,7 +80,7 @@ _usb_uart_pmod_io = [
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_connectors = [
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("pmoda", "N15 L14 K16 K14 N16 L15 J16 J14"), # XADC
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("pmodb", "V8 W8 U7 V7 Y7 Y6 V6 W6"),
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("pmodb", "V8 W8 U7 V7 Y7 Y6 V6 W6"),
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("pmodc", "V15 W15 T11 T10 W14 Y14 T12 U12"),
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("pmodd", "T14 T15 P14 R14 U14 U15 V17 V18"),
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("pmode", "V12 W16 J15 H15 V13 U17 T17 Y17"),
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@ -88,20 +88,20 @@ _connectors = [
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ps7_config = {
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"z7-20" : {
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"PCW_UIPARAM_DDR_PARTNO " : "MT41K256M16 RE-125",
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"PCW_FPGA_FCLK0_ENABLE " : "1",
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"PCW_UART1_BAUD_RATE " : "115200",
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"PCW_EN_UART1 " : "1",
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"PCW_UART1_PERIPHERAL_ENABLE " : "1",
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"PCW_UART1_UART1_IO " : "MIO 48 .. 49",
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"PCW_PRESET_BANK1_VOLTAGE " : "LVCMOS 1.8V",
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"PCW_USE_M_AXI_GP0 " : "1",
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"PCW_USE_S_AXI_GP0 " : "1",
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"PCW_USB0_PERIPHERAL_ENABLE " : "1",
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"PCW_USB0_USB0_IO " : "MIO 28 .. 39",
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"PCW_USB0_RESET_ENABLE " : "1",
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"PCW_USB0_RESET_IO " : "MIO 46",
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"PCW_EN_USB0 " : "1"
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"PCW_UIPARAM_DDR_PARTNO" : "MT41K256M16 RE-125",
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"PCW_FPGA_FCLK0_ENABLE" : "1",
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"PCW_UART1_BAUD_RATE" : "115200",
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"PCW_EN_UART1" : "1",
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"PCW_UART1_PERIPHERAL_ENABLE" : "1",
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"PCW_UART1_UART1_IO" : "MIO 48 .. 49",
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"PCW_PRESET_BANK1_VOLTAGE" : "LVCMOS 1.8V",
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"PCW_USE_M_AXI_GP0" : "1",
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"PCW_USE_S_AXI_GP0" : "1",
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"PCW_USB0_PERIPHERAL_ENABLE" : "1",
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"PCW_USB0_USB0_IO" : "MIO 28 .. 39",
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"PCW_USB0_RESET_ENABLE" : "1",
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"PCW_USB0_RESET_IO" : "MIO 46",
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"PCW_EN_USB0" : "1"
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}
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}
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# Platform -----------------------------------------------------------------------------------------
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@ -115,7 +115,7 @@ class Platform(Xilinx7SeriesPlatform):
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"z7-10": "xc7z010-clg400-1",
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"z7-20": "xc7z020-clg400-1"
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}[variant]
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XilinxPlatform.__init__(self, device, _io, _connectors, toolchain=toolchain)
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Xilinx7SeriesPlatform.__init__(self, device, _io, _connectors, toolchain=toolchain)
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self.add_extension(_ps7_io)
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self.add_extension(_usb_uart_pmod_io)
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self.ps7_config = ps7_config[variant]
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@ -19,7 +19,9 @@ from litex.soc.cores.clock import *
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from litex.soc.integration.soc_core import *
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from litex.soc.integration.builder import *
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from litex.soc.cores.led import LedChaser
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from litex.soc.integration.soc import SoCRegion
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from litex.soc.integration.soc import SoCRegion
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from litex.soc.cores import cpu
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# CRG ----------------------------------------------------------------------------------------------
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class _CRG(LiteXModule):
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@ -29,11 +31,11 @@ class _CRG(LiteXModule):
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# # #
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if use_ps7_clk:
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self.comb += ClockSignal("sys").eq(ClockSignal("ps7"))
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self.comb += ResetSignal("sys").eq(ResetSignal("ps7") | self.rst)
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self.comb += ClockSignal("sys").eq(ClockSignal("ps7"))
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self.comb += ResetSignal("sys").eq(ResetSignal("ps7") | self.rst)
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else:
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self.pll = pll = S7PLL(speedgrade=-1)
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self.comb += pll.reset.eq(self.rst)
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self.pll = pll = S7PLL(speedgrade=-1)
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self.comb += pll.reset.eq(self.rst)
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pll.register_clkin(platform.request("clk125"), 125e6)
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pll.create_clkout(self.cd_sys, sys_clk_freq)
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platform.add_false_path_constraints(self.cd_sys.clk, pll.clkin) # Ignore sys_clk to pll.clkin path created by SoC's rst.
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@ -41,12 +43,12 @@ class _CRG(LiteXModule):
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# BaseSoC ------------------------------------------------------------------------------------------
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class BaseSoC(SoCCore):
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def __init__(self, sys_clk_freq=int(100e6), variant="z7-10", with_ps7=False, with_led_chaser=True, **kwargs):
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def __init__(self, sys_clk_freq=100e6, variant="z7-10", with_ps7=False, with_led_chaser=True, **kwargs):
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platform = digilent_zybo_z7.Platform()
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self.builder = None
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self.builder = None
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# CRG --------------------------------------------------------------------------------------
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use_ps7_clk = (kwargs.get("cpu_type", None) == "zynq7000")
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self.crg = _CRG(platform, sys_clk_freq, use_ps7_clk)
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use_ps7_clk = (kwargs.get("cpu_type", None) == "zynq7000")
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self.crg = _CRG(platform, sys_clk_freq, use_ps7_clk)
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# SoCCore ----------------------------------------------------------------------------------
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if kwargs["uart_name"] == "serial":
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@ -58,18 +60,17 @@ class BaseSoC(SoCCore):
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'csr': 0x4000_0000, # Zynq GP0 default
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}
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SoCCore.__init__(self, platform, sys_clk_freq, ident="LiteX SoC on Zybo Z7", **kwargs)
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# Zynq7000 Integration ---------------------------------------------------------------------
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if kwargs.get("cpu_type", None) == "zynq7000":
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self.cpu.use_rom = True
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if variant == "z7-10":
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# Get and set the pre-generated .xci FIXME: change location? add it to the repository? Make config
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os.makedirs("xci", exist_ok=True)
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os.system("wget https://github.com/litex-hub/litex-boards/files/8339591/zybo_z7_ps7.txt")
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os.system("mv zybo_z7_ps7.txt xci/zybo_z7_ps7.xci")
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self.cpu.set_ps7_xci("xci/zybo_z7_ps7.xci")
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else:
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else:
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self.cpu.set_ps7(name="ps", config = platform.ps7_config)
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# Connect AXI GP0 to the SoC with base address of 0x40000000 (default one)
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@ -90,13 +91,32 @@ class BaseSoC(SoCCore):
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linker = True)
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)
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self.constants["CONFIG_CLOCK_FREQUENCY"] = 666666687
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self.bus.add_region("flash", SoCRegion(origin=0xFC00_0000, size=0x4_0000, mode="rwx"))
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self.bus.add_region("flash", SoCRegion(
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origin = 0xFC00_0000,
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size = 0x4_0000,
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mode = "rwx")
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)
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# PS7 as Slave Integration ---------------------------------------------------------------------
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elif with_ps7:
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#TODO: ps7_slave for each variant
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if variant == "z7-20":
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self.add_ps7()
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self.add_axi_gp_slave()
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cpu_cls = cpu.CPUS["zynq7000"]
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zynq = cpu_cls(self.platform, "standard") # zynq7000 has no variants
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zynq.set_ps7(name="ps", config = platform.ps7_config)
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axi_gp_slave0 = zynq.add_axi_gp_slave(clock_domain = self.crg.cd_sys.name)
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self.submodules += zynq
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self.bus.add_slave(
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name="ps",slave=axi_gp_slave0,
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region=SoCRegion(
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origin=0x2000_0000,
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size=0x2000_0000,
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mode="rwx"
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)
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)
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else:
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#TODO: make config for zybo-z7-10
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raise NotImplementedError
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# Leds -------------------------------------------------------------------------------------
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if with_led_chaser:
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self.leds = LedChaser(
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@ -146,110 +166,23 @@ class BaseSoC(SoCCore):
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#endif
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''')
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def add_ps7(self):
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ps7_tcl = []
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ps7_name = "processing_system"
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ps7_tcl.append(f"set ps7 [create_ip -vendor xilinx.com -name processing_system7 -module_name {ps7_name}]")
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ps7_tcl.append("set_property -dict [list \\")
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for config, value in self.platform.ps7_config.items():
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ps7_tcl.append("CONFIG.{} {} \\".format(config, '{{' + str(value) + '}}'))
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ps7_tcl.append(f"] [get_ips {ps7_name}]")
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ps7_tcl += [
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f"upgrade_ip [get_ips {ps7_name}]",
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f"generate_target all [get_ips {ps7_name}]",
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f"synth_ip [get_ips {ps7_name}]"
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]
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self.platform.toolchain.pre_synthesis_commands += ps7_tcl
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def add_axi_gp_slave(self):
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axi_gpn = axi.AXIInterface(data_width=32, address_width=32, id_width=12)
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#TODO: better mapping/ Different Regions for IOP and DDR
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aw_address = Signal(32)
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ar_address = Signal(32)
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#FIXME: define offsets with csr register?
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self.comb += If(axi_gpn.aw.addr < 0x1ffbffff,
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## DDR
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aw_address.eq(axi_gpn.aw.addr + 0x0008_0000)
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).Else(
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## IOP Register
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aw_address.eq(axi_gpn.aw.addr + 0xe000_0000))
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self.comb += If(axi_gpn.ar.addr < 0x1ffbffff,
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## DDR
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ar_address.eq(axi_gpn.ar.addr + 0x0008_0000)
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).Else(
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## IOP Register
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ar_address.eq(axi_gpn.ar.addr + 0xe000_0000))
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# generate instance of ps7 with ports for axi_s_gp0
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ps7_axi_s_gp0 = Instance("processing_system" ,
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#o_S_AXI_GP0_ARESETN = axi_gpn.a.resetn,
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o_S_AXI_GP0_ARREADY = axi_gpn.ar.ready,
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o_S_AXI_GP0_AWREADY = axi_gpn.aw.ready,
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o_S_AXI_GP0_BVALID = axi_gpn.b.valid,
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o_S_AXI_GP0_RLAST = axi_gpn.r.last,
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o_S_AXI_GP0_RVALID = axi_gpn.r.valid,
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o_S_AXI_GP0_WREADY = axi_gpn.w.ready,
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o_S_AXI_GP0_BRESP = axi_gpn.b.resp,
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o_S_AXI_GP0_RRESP = axi_gpn.r.resp,
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o_S_AXI_GP0_RDATA = axi_gpn.r.data,
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o_S_AXI_GP0_BID = axi_gpn.b.id,
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o_S_AXI_GP0_RID = axi_gpn.r.id,
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i_S_AXI_GP0_ACLK = ClockSignal("sys"),
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i_S_AXI_GP0_ARVALID = axi_gpn.ar.valid,
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i_S_AXI_GP0_AWVALID = axi_gpn.aw.valid,
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i_S_AXI_GP0_BREADY = axi_gpn.b.ready,
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i_S_AXI_GP0_RREADY = axi_gpn.r.ready,
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i_S_AXI_GP0_WLAST = axi_gpn.w.last,
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i_S_AXI_GP0_WVALID = axi_gpn.w.valid,
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i_S_AXI_GP0_ARBURST = axi_gpn.ar.burst,
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i_S_AXI_GP0_ARLOCK = axi_gpn.ar.lock,
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i_S_AXI_GP0_ARSIZE = axi_gpn.ar.size,
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i_S_AXI_GP0_AWBURST = axi_gpn.aw.burst,
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i_S_AXI_GP0_AWLOCK = axi_gpn.aw.lock,
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i_S_AXI_GP0_AWSIZE = axi_gpn.aw.size,
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i_S_AXI_GP0_ARPROT = axi_gpn.ar.prot,
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i_S_AXI_GP0_AWPROT = axi_gpn.aw.prot,
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i_S_AXI_GP0_ARADDR = ar_address,
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i_S_AXI_GP0_AWADDR = aw_address,
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i_S_AXI_GP0_WDATA = axi_gpn.w.data,
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i_S_AXI_GP0_ARCACHE = axi_gpn.ar.cache,
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i_S_AXI_GP0_ARLEN = axi_gpn.ar.len,
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i_S_AXI_GP0_ARQOS = axi_gpn.ar.qos,
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i_S_AXI_GP0_AWCACHE = axi_gpn.aw.cache,
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i_S_AXI_GP0_AWLEN = axi_gpn.aw.len,
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i_S_AXI_GP0_AWQOS = axi_gpn.aw.qos,
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i_S_AXI_GP0_WSTRB = axi_gpn.w.strb,
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i_S_AXI_GP0_ARID = axi_gpn.ar.id,
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i_S_AXI_GP0_AWID = axi_gpn.aw.id,
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i_S_AXI_GP0_WID = axi_gpn.w.id,
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)
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self.specials += ps7_axi_s_gp0
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self.bus.add_slave(name="main_ram",slave=axi_gpn, region=SoCRegion(origin=0x4000_0000, size=0x2000_0000, mode="rwx"))
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# Build --------------------------------------------------------------------------------------------
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def main():
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from litex.soc.integration.soc import LiteXSoCArgumentParser
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parser = LiteXSoCArgumentParser(description="LiteX SoC on Zybo Z7")
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from litex.build.parser import LiteXArgumentParser
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parser = LiteXArgumentParser(description="LiteX SoC on Zybo Z7")
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target_group = parser.add_argument_group(title="Target options")
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target_group.add_argument("--build", action="store_true", help="Build design.")
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target_group.add_argument("--load", action="store_true", help="Load bitstream.")
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target_group.add_argument("--sys-clk-freq", default=125e6, help="System clock frequency.")
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target_group.add_argument("--variant", default="z7-10", help="Board variant (z7-10 or z7-20).")
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target_group.add_argument("--with-ps7", action="store_true", help="Add the PS as slave.")
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target_group.add_argument("--with-ps7", action="store_true", help="Add the PS7 as slave for soft CPUs.")
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builder_args(parser)
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soc_core_args(parser)
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args = parser.parse_args()
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soc = BaseSoC(
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sys_clk_freq = int(float(args.sys_clk_freq)),
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sys_clk_freq = args.sys_clk_freq,
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variant = args.variant,
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with_ps7 = args.with_ps7,
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**soc_core_argdict(args)
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