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targets/icebreaker: simplify arguments and make it closer to others targets.

This commit is contained in:
Florent Kermarrec 2020-03-06 15:11:33 +01:00
parent 992f7066fa
commit 9416ddd84a
1 changed files with 14 additions and 34 deletions
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42
litex_boards/targets/icebreaker.py
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@ -86,8 +86,7 @@ class _CRG(Module, AutoDoc):
class BaseSoC(SoCCore): class BaseSoC(SoCCore):
"""A SoC on iCEBreaker, optionally with a softcore CPU""" """A SoC on iCEBreaker, optionally with a softcore CPU"""
# Statically-define the memory map, to prevent it from shifting across # Statically-define the memory map, to prevent it from shifting across various litex versions.
# various litex versions.
SoCCore.mem_map = { SoCCore.mem_map = {
"rom": 0x00000000, # (default shadow @0x80000000) "rom": 0x00000000, # (default shadow @0x80000000)
"sram": 0x10000000, # (default shadow @0xa0000000) "sram": 0x10000000, # (default shadow @0xa0000000)
@ -106,11 +105,11 @@ class BaseSoC(SoCCore):
""" """
platform = Platform() platform = Platform()
if "cpu_type" not in kwargs: kwargs["cpu_variant"] = "lite"
kwargs["cpu_type"] = None
kwargs["cpu_variant"] = None
else:
kwargs["cpu_reset_address"] = boot_vector kwargs["cpu_reset_address"] = boot_vector
if debug:
kwargs["uart_name"] = "crossover"
kwargs["cpu_variant"] = "lite+debug"
clk_freq = int(12e6) clk_freq = int(12e6)
@ -118,15 +117,7 @@ class BaseSoC(SoCCore):
kwargs["integrated_sram_size"] = 0 kwargs["integrated_sram_size"] = 0
kwargs["integrated_rom_size"] = 0 kwargs["integrated_rom_size"] = 0
if debug: SoCCore.__init__(self, platform, clk_freq, **kwargs)
kwargs["uart_name"] = "crossover"
if kwargs["cpu_type"] == "vexriscv":
kwargs["cpu_variant"] = kwargs["cpu_variant"] + "+debug"
SoCCore.__init__(self, platform, clk_freq,
with_uart=True,
with_ctrl=True,
**kwargs)
# If there is a VexRiscv CPU, add a fake ROM that simply tells the CPU # If there is a VexRiscv CPU, add a fake ROM that simply tells the CPU
# to jump to the given address. # to jump to the given address.
@ -200,28 +191,17 @@ def main():
parser = argparse.ArgumentParser(description="LiteX SoC on iCEBreaker") parser = argparse.ArgumentParser(description="LiteX SoC on iCEBreaker")
parser.add_argument("--nextpnr-seed", default=0, help="Seed to use in Nextpnr") parser.add_argument("--nextpnr-seed", default=0, help="Seed to use in Nextpnr")
parser.add_argument("--nextpnr-placer", default="heap", choices=["sa", "heap"], help="Placer implementation to use in Nextpnr") parser.add_argument("--nextpnr-placer", default="heap", choices=["sa", "heap"], help="Placer implementation to use in Nextpnr")
parser.add_argument(
"--cpu", action="store_true", help="Add a CPU to the build"
)
builder_args(parser) builder_args(parser)
soc_core_args(parser) soc_core_args(parser)
args = parser.parse_args() args = parser.parse_args()
kwargs = builder_argdict(args) soc = BaseSoC(debug=True, **soc_core_argdict(args))
if args.cpu:
kwargs["cpu_type"] = "vexriscv"
kwargs["cpu_variant"] = "lite"
soc = BaseSoC(debug=True, **kwargs)
soc.set_yosys_nextpnr_settings(nextpnr_seed=args.nextpnr_seed, nextpnr_placer=args.nextpnr_placer) soc.set_yosys_nextpnr_settings(nextpnr_seed=args.nextpnr_seed, nextpnr_placer=args.nextpnr_placer)
kwargs = builder_argdict(args) # Don't build software -- we don't include it since we just jump to SPI flash.
builder_kwargs = builder_argdict(args)
# Don't build software -- we don't include it since we just jump builder_kwargs["compile_software"] = False
# to SPI flash. builder = Builder(soc, **builder_kwargs)
kwargs["compile_software"] = False
builder = Builder(soc, **kwargs)
builder.build() builder.build()