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targets: Minor cleanup, make sure all targets can be built with default settings.

This commit is contained in:
Florent Kermarrec 2021-03-29 16:22:39 +02:00
parent 1ca8ef97a1
commit 9417044584
6 changed files with 24 additions and 25 deletions
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1
litex_boards/targets/1bitsquared_icebreaker.py
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@ -122,7 +122,6 @@ def flash(bios_flash_offset):
prog = IceStormProgrammer()
prog.flash(bios_flash_offset, "build/icebreaker/software/bios/bios.bin")
prog.flash(0x00000000, "build/icebreaker/gateware/icebreaker.bin")
exit()
# Build --------------------------------------------------------------------------------------------

6
litex_boards/targets/colorlight_i5.py
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@ -27,7 +27,7 @@ from litex.soc.cores.led import LedChaser
from litex.soc.interconnect.csr import *
from litedram.modules import M12L64322A
from litedram.modules import M12L64322A # Compatible with EM638325-6H.
from litedram.phy import GENSDRPHY, HalfRateGENSDRPHY
from liteeth.phy.ecp5rgmii import LiteEthPHYRGMII
@ -129,11 +129,9 @@ class BaseSoC(SoCCore):
if not self.integrated_main_ram_size:
sdrphy_cls = HalfRateGENSDRPHY if sdram_rate == "1:2" else GENSDRPHY
self.submodules.sdrphy = sdrphy_cls(platform.request("sdram"))
# if board == "i5" and revision == "7.0":
sdram_cls = M12L64322A # compat with EM638325-6H
self.add_sdram("sdram",
phy = self.sdrphy,
module = sdram_cls(sys_clk_freq, sdram_rate),
module = M12L64322A(sys_clk_freq, sdram_rate),
l2_cache_size = kwargs.get("l2_size", 8192)
)

2
litex_boards/targets/numato_aller.py
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@ -60,6 +60,8 @@ class BaseSoC(SoCCore):
platform = aller.Platform()
# SoCCore ----------------------------------------------------------------------------------
if kwargs.get("uart_name", "serial") == "serial":
kwargs["uart_name"] = "crossover" # Defaults to Crossover UART.
SoCCore.__init__(self, platform, sys_clk_freq,
ident = "LiteX SoC on Aller",
ident_version = True,

2
litex_boards/targets/sqrl_fk33.py
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@ -47,6 +47,8 @@ class BaseSoC(SoCCore):
platform = fk33.Platform()
# SoCCore ----------------------------------------------------------------------------------
if kwargs.get("uart_name", "serial") == "serial":
kwargs["uart_name"] = "jtag_uart" # Defaults to JTAG-UART.
SoCCore.__init__(self, platform, sys_clk_freq,
ident = "LiteX SoC on FK33",
ident_version = True,

17
litex_boards/targets/terasic_sockit.py
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@ -120,14 +120,15 @@ class BaseSoC(SoCCore):
self.submodules.crg = _CRG(platform, sys_clk_freq, with_sdram=mister_sdram != None, sdram_rate=sdram_rate)
# SDR SDRAM --------------------------------------------------------------------------------
sdrphy_cls = HalfRateGENSDRPHY if sdram_rate == "1:2" else GENSDRPHY
sdrphy_mod = {"xs_v22": W9825G6KH6, "xs_v24": AS4C32M16}
self.submodules.sdrphy = sdrphy_cls(platform.request("sdram"), sys_clk_freq)
self.add_sdram("sdram",
phy = self.sdrphy,
module = sdrphy_mod(sys_clk_freq, sdram_rate),
l2_cache_size = kwargs.get("l2_size", 8192)
)
if mister_sdram is not None:
sdrphy_cls = HalfRateGENSDRPHY if sdram_rate == "1:2" else GENSDRPHY
sdrphy_mod = {"xs_v22": W9825G6KH6, "xs_v24": AS4C32M16}[mister_sdram]
self.submodules.sdrphy = sdrphy_cls(platform.request("sdram"), sys_clk_freq)
self.add_sdram("sdram",
phy = self.sdrphy,
module = sdrphy_mod(sys_clk_freq, sdram_rate),
l2_cache_size = kwargs.get("l2_size", 8192)
)
# Video Terminal ---------------------------------------------------------------------------
if with_video_terminal:

21
litex_boards/targets/ztex213.py
View File

@ -3,17 +3,16 @@
#
# This file is part of LiteX-Boards.
#
# Support for the ZTEX USB-FGPA Module 2.13:
# <https://www.ztex.de/usb-fpga-2/usb-fpga-2.13.e.html>
# With (no-so-optional) expansion, either the ZTEX Debug board:
# <https://www.ztex.de/usb-fpga-2/debug.e.html>
# Or the SBusFPGA adapter board:
# <https://github.com/rdolbeau/SBusFPGA>
#
# Copyright (c) 2015-2019 Florent Kermarrec <florent@enjoy-digital.fr>
# Copyright (c) 2020-2021 Romain Dolbeau <romain@dolbeau.org>
# SPDX-License-Identifier: BSD-2-Clause
# Support for the ZTEX USB-FGPA Module 2.13:https://www.ztex.de/usb-fpga-2/usb-fpga-2.13.e.html.
# With (no-so-optional) expansion, either the ZTEX Debug board:
# https://www.ztex.de/usb-fpga-2/debug.e.html
# Or the SBusFPGA adapter board:
# https://github.com/rdolbeau/SBusFPGA
import os
import argparse
@ -44,7 +43,6 @@ class _CRG(Module):
clk48 = platform.request("clk48")
self.submodules.pll = pll = S7MMCM(speedgrade=-1)
# self.comb += pll.reset.eq(~platform.request("cpu_reset"))
pll.register_clkin(clk48, 48e6)
pll.create_clkout(self.cd_sys, sys_clk_freq)
pll.create_clkout(self.cd_sys4x, 4*sys_clk_freq)
@ -84,7 +82,7 @@ class BaseSoC(SoCCore):
sys_clk_freq = sys_clk_freq)
self.add_sdram("sdram",
phy = self.ddrphy,
module = MT41J128M16(sys_clk_freq, "1:4"), #MT41J128M16XX-125
module = MT41J128M16(sys_clk_freq, "1:4"),
l2_cache_size = kwargs.get("l2_size", 8192)
)
@ -105,16 +103,15 @@ def main():
parser.add_argument("--with-sdcard", action="store_true", help="Enable SDCard support")
builder_args(parser)
soc_core_args(parser)
#soc_core_args(parser)
vivado_build_args(parser)
args = parser.parse_args()
soc = BaseSoC(sys_clk_freq=int(float(args.sys_clk_freq)), expansion=args.expansion, **soc_core_argdict(args))
assert not (args.with_spi_sdcard and args.with_sdcard)
if args.with_spi_sdcard:
soc.add_spi_sdcard() #sbus only
soc.add_spi_sdcard() # SBus only
if args.with_sdcard:
soc.add_sdcard() #sbus only
soc.add_sdcard() # SBus only
builder = Builder(soc, **builder_argdict(args))
builder.build(**vivado_build_argdict(args), run=args.build)