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marble/marble_mini: Add berkeleylab prefix.

This commit is contained in:
Florent Kermarrec 2021-11-04 18:42:16 +01:00
parent 5e5ae880a4
commit 9543b5efae
4 changed files with 624 additions and 3 deletions
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1
litex_boards/__init__.py
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@ -8,6 +8,7 @@ import importlib
vendors = [
"1bitsquared",
"antmicro",
"berkeleylab",
"colorlight",
"decklink",
"digilent",

347
litex_boards/platforms/berkeleylab_marble.py Normal file
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@ -0,0 +1,347 @@
#
# This file is part of LiteX-Boards.
#
# Copyright (c) 2021 Vamsi K Vytla <vamsi.vytla@gmail.com>
# Copyright (c) 2021 Michael Betz <michibetz@gmail.com>
# SPDX-License-Identifier: BSD-2-Clause
#
# Marble is a dual FMC FPGA carrier board developed for general purpose use in
# particle accelerator electronics instrumentation. It is currently under
# development and the base platform for two accelerator projects at DOE: ALS-U
# (the Advanced Light Source Upgrade at LBNL and the LCLS-II HE (the Linac
# Coherent Light Source II High Energy upgrade).
# https://github.com/BerkeleyLab/Marble
#
# Generated by gen_marble.py (git 4a42959)
# https://github.com/yetifrisstlama/litex_test_project/blob/4a42959/xdc/gen_marble.py
# Pin numbers extracted from a .xdc file, which was auto-generated from
# the Kicad Schematic.
from litex.build.generic_platform import *
from litex.build.xilinx import XilinxPlatform
from litex.build.openocd import OpenOCD
# IOs ----------------------------------------------------------------------------------------------
_io = [
("eth", 0,
Subsignal("rst_n", Pins("B9"), IOStandard("LVCMOS25")),
Subsignal("rx_ctl", Pins("J11"), IOStandard("LVCMOS25")),
Subsignal("rx_data", Pins("J10 J8 H8 H9"), IOStandard("LVCMOS25")),
Subsignal("tx_ctl", Pins("C9"), IOStandard("LVCMOS25")),
Subsignal("tx_data", Pins("H11 H12 D8 D9"), IOStandard("LVCMOS25")),
),
("eth_clocks", 0,
Subsignal("tx", Pins("F10"), IOStandard("LVCMOS25")),
Subsignal("rx", Pins("E11"), IOStandard("LVCMOS25")),
),
# Tunable VCXO. Warning: Non clock-capable pin
("clk20", 0, Pins("W11"), IOStandard("LVCMOS15")),
# Main system clock. White rabbit compatible
("clk125", 0,
Subsignal("p", Pins("AC9"), IOStandard("DIFF_SSTL15")),
Subsignal("n", Pins("AD9"), IOStandard("DIFF_SSTL15")),
),
# 4x Multi gigabit clocks from cross-point switch, source configured by MMC
("clkmgt", 0,
Subsignal("p", Pins("D6"), IOStandard("DIFF_SSTL15")),
Subsignal("n", Pins("D5"), IOStandard("DIFF_SSTL15")),
),
("clkmgt", 1,
Subsignal("p", Pins("F6"), IOStandard("DIFF_SSTL15")),
Subsignal("n", Pins("F5"), IOStandard("DIFF_SSTL15")),
),
("clkmgt", 2,
Subsignal("p", Pins("H6"), IOStandard("DIFF_SSTL15")),
Subsignal("n", Pins("H5"), IOStandard("DIFF_SSTL15")),
),
("clkmgt", 3,
Subsignal("p", Pins("K6"), IOStandard("DIFF_SSTL15")),
Subsignal("n", Pins("K5"), IOStandard("DIFF_SSTL15")),
),
# 2x LED: LD16 and LD17
("user_led", 0, Pins("Y13"), IOStandard("LVCMOS15")),
("user_led", 1, Pins("V12"), IOStandard("LVCMOS15")),
# USB UART
("serial", 0,
Subsignal("tx", Pins("K15"), IOStandard("LVCMOS25")),
Subsignal("rts", Pins("M16"), IOStandard("LVCMOS25")),
Subsignal("rx", Pins("C16"), IOStandard("LVCMOS25")),
),
# I2C system bus, shared access with microcontroller
# connected to TCA9548A I2C-multiplexer
("i2c_fpga", 0,
Subsignal("scl", Pins("B16"), IOStandard("LVCMOS25")),
Subsignal("sda", Pins("A17"), IOStandard("LVCMOS25")),
Subsignal("rst", Pins("B19"), IOStandard("LVCMOS25")),
),
# QSPI Boot Flash
# access clock via STARTUPE2 primitive, wp_n may not be connected.
("spiflash", 0,
Subsignal("cs_n", Pins("C23"), IOStandard("LVCMOS25")),
Subsignal("mosi", Pins("B24"), IOStandard("LVCMOS25")),
Subsignal("miso", Pins("A25"), IOStandard("LVCMOS25")),
Subsignal("wp_n", Pins("B22"), IOStandard("LVCMOS25")),
),
# 2x DAC for white rabbit frequency control
("wr_dac", 0,
Subsignal("clk", Pins("V11"), IOStandard("LVCMOS15")),
Subsignal("din", Pins("Y10"), IOStandard("LVCMOS15")),
Subsignal("synca", Pins("W10"), IOStandard("LVCMOS15")),
Subsignal("syncb", Pins("Y11"), IOStandard("LVCMOS15")),
),
# DDR3 module
("ddram", 0,
Subsignal("a", Pins("AC8 AB10 AA9 AA10 AD10 AC12 AB11 AC11 AF13 AE13 AE10 AD11 AA12 AE8 AB12 AD13"), IOStandard("SSTL15")),
Subsignal("ba", Pins("AF10 AD8 AC13"), IOStandard("SSTL15")),
Subsignal("ras_n", Pins("AB7"), IOStandard("SSTL15")),
Subsignal("cas_n", Pins("AF8"), IOStandard("SSTL15")),
Subsignal("we_n", Pins("AF9"), IOStandard("SSTL15")),
Subsignal("cs_n", Pins("AC7"), IOStandard("SSTL15")),
Subsignal("dm", Pins("AF17 W15 AC19 AA15 AC3 AD4 W1 U7"), IOStandard("SSTL15")),
Subsignal("dq", Pins("AF20 AF19 AE17 AE15 AD16 AD15 AF15 AF14 V17 Y17 V18 V19 V16 W16 V14 W14 AA20 AD19 AB17 AC17 AA19 AB19 AD18 AC18 AA18 AB16 AA14 AD14 AB15 AA17 AC14 AB14 AD6 AB6 Y6 AC4 AC6 AB4 AA4 Y5 AF2 AE2 AE1 AD1 AE5 AE6 AF3 AE3 AA3 AC2 V2 V1 AB2 Y3 Y2 Y1 W3 V4 U2 U1 V6 V3 U6 U5"), IOStandard("SSTL15")),
Subsignal("dqs_p", Pins("AE18 W18 AD20 Y15 AA5 AF5 AB1 W6"), IOStandard("DIFF_SSTL15")),
Subsignal("dqs_n", Pins("AF18 W19 AE20 Y16 AB5 AF4 AC1 W5"), IOStandard("DIFF_SSTL15")),
Subsignal("clk_p", Pins("AE12"), IOStandard("DIFF_SSTL15")),
Subsignal("clk_n", Pins("AF12"), IOStandard("DIFF_SSTL15")),
Subsignal("cke", Pins("AA13"), IOStandard("SSTL15")),
Subsignal("odt", Pins("AB9"), IOStandard("SSTL15")),
Subsignal("reset_n", Pins("Y12"), IOStandard("SSTL15")),
),
]
# Connectors ---------------------------------------------------------------------------------------
_connectors = [
("fmca", {
"CLK0_M2C_N": "E17",
"CLK0_M2C_P": "F17",
"CLK1_M2C_N": "D18",
"CLK1_M2C_P": "E18",
"LA0_N": "H18",
"LA0_P": "H17",
"LA1_N": "F18",
"LA1_P": "G17",
"LA2_N": "J20",
"LA2_P": "K20",
"LA3_N": "L18",
"LA3_P": "M17",
"LA4_N": "G20",
"LA4_P": "H19",
"LA5_N": "E20",
"LA5_P": "F19",
"LA6_N": "L20",
"LA6_P": "L19",
"LA7_N": "D20",
"LA7_P": "D19",
"LA8_N": "F20",
"LA8_P": "G19",
"LA9_N": "J19",
"LA9_P": "J18",
"LA10_N": "G16",
"LA10_P": "H16",
"LA11_N": "K18",
"LA11_P": "L17",
"LA12_N": "F15",
"LA12_P": "G15",
"LA13_N": "D16",
"LA13_P": "D15",
"LA14_N": "E16",
"LA14_P": "E15",
"LA15_N": "J16",
"LA15_P": "J15",
"LA16_N": "K17",
"LA16_P": "K16",
"LA17_N": "D10",
"LA17_P": "E10",
"LA18_N": "C11",
"LA18_P": "C12",
"LA19_N": "G14",
"LA19_P": "H14",
"LA20_N": "A15",
"LA20_P": "B15",
"LA21_N": "D13",
"LA21_P": "D14",
"LA22_N": "A14",
"LA22_P": "B14",
"LA23_N": "F12",
"LA23_P": "G12",
"LA24_N": "A8",
"LA24_P": "A9",
"LA25_N": "G9",
"LA25_P": "G10",
"LA26_N": "E12",
"LA26_P": "E13",
"LA27_N": "F13",
"LA27_P": "F14",
"LA28_N": "H13",
"LA28_P": "J13",
"LA29_N": "F8",
"LA29_P": "F9",
"LA30_N": "B11",
"LA30_P": "B12",
"LA31_N": "A12",
"LA31_P": "A13",
"LA32_N": "C13",
"LA32_P": "C14",
"LA33_N": "A10",
"LA33_P": "B10",
}),
("fmcb", {
"CLK0_M2C_N": "AA24",
"CLK0_M2C_P": "Y23",
"CLK1_M2C_N": "E23",
"CLK1_M2C_P": "F22",
"HA00_CC_N": "N22",
"HA00_CC_P": "N21",
"HA01_CC_N": "P21",
"HA01_CC_P": "R21",
"HA02_N": "U20",
"HA02_P": "U19",
"HA03_N": "T19",
"HA03_P": "T18",
"HA04_N": "R17",
"HA04_P": "R16",
"HA05_N": "N17",
"HA05_P": "P16",
"HA06_N": "P18",
"HA06_P": "R18",
"HA07_N": "T25",
"HA07_P": "T24",
"HA08_N": "T23",
"HA08_P": "T22",
"HA09_N": "T17",
"HA09_P": "U17",
"HA10_N": "K26",
"HA10_P": "K25",
"HA11_N": "M19",
"HA11_P": "N18",
"HA12_N": "L24",
"HA12_P": "M24",
"HA13_N": "R20",
"HA13_P": "T20",
"HA14_N": "P20",
"HA14_P": "P19",
"HA15_N": "P25",
"HA15_P": "R25",
"HA16_N": "P26",
"HA16_P": "R26",
"HA17_CC_N": "R23",
"HA17_CC_P": "R22",
"HA18_N": "M22",
"HA18_P": "M21",
"HA19_N": "M20",
"HA19_P": "N19",
"HA20_N": "N23",
"HA20_P": "P23",
"HA21_N": "N24",
"HA21_P": "P24",
"HA22_N": "M26",
"HA22_P": "N26",
"HA23_N": "L25",
"HA23_P": "M25",
"LA0_N": "AA22",
"LA0_P": "Y22",
"LA1_N": "AB24",
"LA1_P": "AA23",
"LA2_N": "AF22",
"LA2_P": "AE22",
"LA3_N": "AE26",
"LA3_P": "AD26",
"LA4_N": "W21",
"LA4_P": "V21",
"LA5_N": "AC26",
"LA5_P": "AB26",
"LA6_N": "AD24",
"LA6_P": "AD23",
"LA7_N": "AC22",
"LA7_P": "AB22",
"LA8_N": "AC24",
"LA8_P": "AC23",
"LA9_N": "V26",
"LA9_P": "U26",
"LA10_N": "AF23",
"LA10_P": "AE23",
"LA11_N": "W24",
"LA11_P": "W23",
"LA12_N": "AB25",
"LA12_P": "AA25",
"LA13_N": "V24",
"LA13_P": "V23",
"LA14_N": "U25",
"LA14_P": "U24",
"LA15_N": "V22",
"LA15_P": "U22",
"LA16_N": "W26",
"LA16_P": "W25",
"LA17_N": "F23",
"LA17_P": "G22",
"LA18_N": "F24",
"LA18_P": "G24",
"LA19_N": "J23",
"LA19_P": "K23",
"LA20_N": "K22",
"LA20_P": "L22",
"LA21_N": "H22",
"LA21_P": "J21",
"LA22_N": "D25",
"LA22_P": "E25",
"LA23_N": "H24",
"LA23_P": "H23",
"LA24_N": "J25",
"LA24_P": "J24",
"LA25_N": "D24",
"LA25_P": "D23",
"LA26_N": "E26",
"LA26_P": "F25",
"LA27_N": "G21",
"LA27_P": "H21",
"LA28_N": "G26",
"LA28_P": "G25",
"LA29_N": "H26",
"LA29_P": "J26",
"LA30_N": "C26",
"LA30_P": "D26",
"LA31_N": "E22",
"LA31_P": "E21",
"LA32_N": "A20",
"LA32_P": "B20",
"LA33_N": "B21",
"LA33_P": "C21",
}),
("pmoda", "C24 C22 L23 D21 K21 C18 C19 C17"),
("pmodb", "AE7 V7 Y7 AF7 V8 AA8 Y8 W9"),
]
# Platform -----------------------------------------------------------------------------------------
class Platform(XilinxPlatform):
default_clk_name = "clk125"
default_clk_period = 1e9 / 125e6
def __init__(self):
XilinxPlatform.__init__(self, "xc7k160t-ffg676-2", _io, _connectors, toolchain="vivado")
self.toolchain.bitstream_commands = [
"set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]"
]
self.toolchain.additional_commands = [
"write_cfgmem -force -format bin -interface spix4 -size 16 -loadbit \"up 0x0 {build_name}.bit\" -file {build_name}.bin"
]
# from pin_map.csv: This is a frequency source, not a phase source, so having it enter on a non-CC pin is OK.
self.add_platform_command("set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk20_IBUF]")
self.add_platform_command("set_property CONFIG_VOLTAGE 2.5 [current_design]")
self.add_platform_command("set_property CFGBVS VCCO [current_design]")
# TODO
# self.add_platform_command("set_property INTERNAL_VREF 0.675 [get_iobanks 35]")
def create_programmer(self):
# same file works for marble mini and for marble
return OpenOCD("openocd_marblemini.cfg")
def do_finalize(self, fragment):
XilinxPlatform.do_finalize(self, fragment)
self.add_period_constraint(self.lookup_request("clk20", loose=True), 1e9/20e6)
self.add_period_constraint(self.lookup_request("clk125", loose=True), 1e9/125e6)

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litex_boards/platforms/berkeleylab_marblemini.py Normal file
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@ -0,0 +1,273 @@
#
# This file is part of LiteX-Boards.
#
# Copyright (c) 2020 Vamsi K Vytla <vamsi.vytla@gmail.com>
# SPDX-License-Identifier: BSD-2-Clause
# The Marble-Mini is a simple AMC FMC carrier board with SFP, 2x FMC, PoE, DDR3:
# https://github.com/BerkeleyLab/Marble-Mini
from litex.build.generic_platform import *
from litex.build.xilinx import XilinxPlatform, VivadoProgrammer
from litex.build.openocd import OpenOCD
# TODO:
# - Add the TMDS lanes for the HDMI connector.
# - Populate the SFPs.
# - verify period constraint on mgt_clk1.
# IOs ----------------------------------------------------------------------------------------------
_io = [
# Clk / Rst
("clk20_vcxo", 0, Pins("D17"), IOStandard("LVCMOS33")),
("clk20_vcxo_en", 0, Pins("E13"), IOStandard("LVCMOS33"), Misc("PULLUP=TRUE")), # Set it to 1 to enable clk20_-vcxo.
("mgt_clk", 0,
Subsignal("p", Pins("F6")),
Subsignal("n", Pins("E6"))
),
("mgt_clk", 1,
Subsignal("p", Pins("F10")),
Subsignal("n", Pins("E10"))
),
# Serial
("serial", 0,
Subsignal("rts", Pins("W9")),
Subsignal("rx", Pins("U7")),
Subsignal("tx", Pins("Y9")),
IOStandard("LVCMOS25")
),
# RGMII Ethernet
("eth_clocks", 0,
Subsignal("tx", Pins("J15")),
Subsignal("rx", Pins("L19")),
IOStandard("LVCMOS25")
),
("eth", 0,
Subsignal("rst_n", Pins("M17")),
Subsignal("rx_ctl", Pins("H15")),
Subsignal("rx_data", Pins("K13 H14 J14 K14")),
Subsignal("tx_ctl", Pins("J16")),
Subsignal("tx_data", Pins("G15 G16 G13 H13")),
IOStandard("LVCMOS25"),
),
# DDR3 SDRAM
("ddram", 0,
Subsignal("a", Pins(
"L6 M5 P6 K6 M1 M3 N2 M6",
"P1 P2 L4 N5 L3 R1 N3 E3"),
IOStandard("SSTL135")),
Subsignal("ba", Pins("L5 M2 N4"), IOStandard("SSTL135")),
Subsignal("ras_n", Pins("J4"), IOStandard("SSTL135")),
Subsignal("cas_n", Pins("J6"), IOStandard("SSTL135")),
Subsignal("we_n", Pins("K3"), IOStandard("SSTL135")),
Subsignal("dm", Pins("G2 E2"), IOStandard("SSTL135")),
Subsignal("dq", Pins(
"G3 J1 H4 H5 H2 K1 H3 J5",
"G1 B1 F1 F3 C2 A1 D2 B2"),
IOStandard("SSTL135")),
Subsignal("dqs_p", Pins("K2 E1"), IOStandard("DIFF_SSTL135")),
Subsignal("dqs_n", Pins("J2 D1"), IOStandard("DIFF_SSTL135")),
Subsignal("clk_p", Pins("P5"), IOStandard("DIFF_SSTL135")),
Subsignal("clk_n", Pins("P4"), IOStandard("DIFF_SSTL135")),
Subsignal("cke", Pins("L1"), IOStandard("SSTL135")),
Subsignal("odt", Pins("K4"), IOStandard("SSTL135")),
# Subsignal("cs_n", Pins(""), IOStandard("SSTL135")),
Subsignal("reset_n", Pins("G4"), IOStandard("SSTL135"))
),
]
# Connectors ---------------------------------------------------------------------------------------
_connectors = [
("PMOD0", "C18 D22 E22 G21 D21 E21 F21 G22"),
("PMOD1", "F13 C14 C15 D16 F14 F15 F16 E16"),
("FMC1_LPC", {
"CLK0_M2C_N": "W20",
"CLK0_M2C_P": "W19",
"CLK1_M2C_N": "Y19",
"CLK1_M2C_P": "Y18",
"LA00_N": "V20",
"LA00_P": "U20",
"LA01_N": "V19",
"LA01_P": "V18",
"LA02_N": "R16",
"LA02_P": "P15",
"LA03_N": "N14",
"LA03_P": "N13",
"LA04_N": "W17",
"LA04_P": "V17",
"LA05_N": "R19",
"LA05_P": "P19",
"LA06_N": "AB18",
"LA06_P": "AA18",
"LA07_N": "AA21",
"LA07_P": "AA20",
"LA08_N": "P17",
"LA08_P": "N17",
"LA09_N": "T18",
"LA09_P": "R18",
"LA10_N": "AB20",
"LA10_P": "AA19",
"LA11_N": "R17",
"LA11_P": "P16",
"LA12_N": "U18",
"LA12_P": "U17",
"LA13_N": "W22",
"LA13_P": "W21",
"LA14_N": "AB22",
"LA14_P": "AB21",
"LA15_N": "Y22",
"LA15_P": "Y21",
"LA16_N": "R14",
"LA16_P": "P14",
"LA17_N_CC": "K19",
"LA17_P_CC": "K18",
"LA18_N_CC": "H19",
"LA18_P_CC": "J19",
"LA19_N": "J17",
"LA19_P": "K17",
"LA20_N": "L15",
"LA20_P": "L14",
"LA21_N": "N19",
"LA21_P": "N18",
"LA22_N": "L21",
"LA22_P": "M21",
"LA23_N": "M20",
"LA23_P": "N20",
"LA24_N": "H18",
"LA24_P": "H17",
"LA25_N": "L18",
"LA25_P": "M18",
"LA26_N": "G20",
"LA26_P": "H20",
"LA27_N": "M22",
"LA27_P": "N22",
"LA28_N": "M16",
"LA28_P": "M15",
"LA29_N": "K22",
"LA29_P": "K21",
"LA30_N": "K16",
"LA30_P": "L16",
"LA31_N": "H22",
"LA31_P": "J22",
"LA32_N": "G18",
"LA32_P": "G17",
"LA33_N": "J21",
"LA33_P": "J20"
}),
("FMC2_LPC", {
"CLK0_M2C_N": "W4",
"CLK0_M2C_P": "V4",
"CLK1_M2C_N": "T4",
"CLK1_M2C_P": "R4",
"LA00_N": "U5",
"LA00_P": "T5",
"LA01_N": "AA4",
"LA01_P": "Y4",
"LA02_N": "V3",
"LA02_P": "U3",
"LA03_N": "V2",
"LA03_P": "U2",
"LA04_N": "V5",
"LA04_P": "U6",
"LA05_N": "T6",
"LA05_P": "R6",
"LA06_N": "U1",
"LA06_P": "T1",
"LA07_N": "V8",
"LA07_P": "V9",
"LA08_N": "Y2",
"LA08_P": "W2",
"LA09_N": "AA3",
"LA09_P": "Y3",
"LA10_N": "Y1",
"LA10_P": "W1",
"LA11_N": "AA6",
"LA11_P": "Y6",
"LA12_N": "W5",
"LA12_P": "W6",
"LA13_N": "W7",
"LA13_P": "V7",
"LA14_N": "AB1",
"LA14_P": "AA1",
"LA15_N": "AB5",
"LA15_P": "AA5",
"LA16_N": "AB2",
"LA16_P": "AB3",
"LA17_N": "W12",
"LA17_P": "W11",
"LA18_N": "V14",
"LA18_P": "V13",
"LA19_N": "Y12",
"LA19_P": "Y11",
"LA20_N": "AA11",
"LA20_P": "AA10",
"LA21_N": "AA14",
"LA21_P": "Y13",
"LA22_N": "W16",
"LA22_P": "W15",
"LA23_N": "W10",
"LA23_P": "V10",
"LA24_N": "Y14",
"LA24_P": "W14",
"LA25_N": "AB12",
"LA25_P": "AB11",
"LA26_N": "AA16",
"LA26_P": "Y16",
"LA27_N": "AB10",
"LA27_P": "AA9",
"LA28_N": "T15",
"LA28_P": "T14",
"LA29_N": "U16",
"LA29_P": "T16",
"LA30_N": "V15",
"LA30_P": "U15",
"LA31_N": "AB13",
"LA31_P": "AA13",
"LA32_N": "AB15",
"LA32_P": "AA15",
"LA33_N": "AB17",
"LA33_P": "AB16"
})
]
_pmod0_pins = ["PMOD0:{}".format(i) for i in range(8)]
_pmod1_pins = ["PMOD1:{}".format(i) for i in range(8)]
break_off_pmod = [
("pmod0", 0, Pins(*_pmod0_pins), IOStandard("LVCMOS33")),
("pmod1", 0, Pins(*_pmod1_pins), IOStandard("LVCMOS33")),
]
# Platform -----------------------------------------------------------------------------------------
class Platform(XilinxPlatform):
default_clk_name = "clk20_vcxo"
default_clk_period = 1e9/20e6
def __init__(self):
XilinxPlatform.__init__(self, "xc7a100t-2fgg484", _io, _connectors, toolchain="vivado")
self.toolchain.bitstream_commands = [
"set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]"
]
self.toolchain.additional_commands = [
"write_cfgmem -force -format bin -interface spix4 -size 16 -loadbit \"up 0x0 {build_name}.bit\" -file {build_name}.bin"
]
self.add_platform_command("set_property INTERNAL_VREF 0.675 [get_iobanks 35]")
self.add_platform_command("set_property CFGBVS VCCO [current_design]")
self.add_platform_command("set_property CONFIG_VOLTAGE 3.3 [current_design]")
def create_programmer(self):
return OpenOCD("openocd_marblemini.cfg")
def do_finalize(self, fragment):
XilinxPlatform.do_finalize(self, fragment)
self.add_period_constraint(self.lookup_request("clk20_vcxo", loose=True), 1e9/20e6)
self.add_period_constraint(self.lookup_request("mgt_clk", 0, loose=True), 1e9/125e6)
self.add_period_constraint(self.lookup_request("mgt_clk", 1, loose=True), 1e9/125e6)
self.add_period_constraint(self.lookup_request("eth_clocks:rx", loose=True), 1e9/125e6)

6
litex_boards/targets/marble.py → litex_boards/targets/berkeleylab_marble.py Normal file → Executable file
View File

@ -29,7 +29,7 @@ import argparse
from migen import *
from litex_boards.platforms import marble
from litex_boards.platforms import berkeleylab_marble
from litex.soc.cores.clock import *
from litex.soc.integration.soc_core import *
@ -80,11 +80,11 @@ class BaseSoC(SoCCore):
spd_dump=None,
**kwargs
):
platform = marble.Platform()
platform = berkeleylab_marble.Platform()
# SoCCore ----------------------------------------------------------------------------------
SoCCore.__init__(self, platform, sys_clk_freq,
ident = "LiteX SoC on Marble",
ident = "LiteX SoC on Berkeley-Lab Marble",
ident_version = True,
**kwargs)