Hardware
/
litex-boards
mirror of https://github.com/litex-hub/litex-boards.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

platforms/sds1104xe: fix ddram IOStandard (SSTL15, thanks @tmbinc) and add INTERNAL_VREF on ddram banks.

This commit is contained in:
Florent Kermarrec 2021-02-16 17:32:41 +01:00
parent 9baa9d5d83
commit 975150ca68
1 changed files with 17 additions and 15 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

32
litex_boards/platforms/sds1104xe.py
View File

@ -71,31 +71,31 @@ _io = [ # Documented by https://github.com/360nosc0pe project.
Subsignal("a", Pins(
"J21 K18 J18 R16 P16 T18 R18 T19",
"R19 P18 P17 P15 N15"),
IOStandard("SSTL135")),
Subsignal("ba", Pins("K21 J20 J22"), IOStandard("SSTL135")),
Subsignal("ras_n", Pins("L21"), IOStandard("SSTL135")),
Subsignal("cas_n", Pins("L22"), IOStandard("SSTL135")),
Subsignal("we_n", Pins("K19"), IOStandard("SSTL135")),
#Subsignal("cs_n", Pins(""), IOStandard("SSTL135")), # Pulled low.
#Subsignal("dm", Pins(""), IOStandard("SSTL135")), # Pulled low.
IOStandard("SSTL15")),
Subsignal("ba", Pins("K21 J20 J22"), IOStandard("SSTL15")),
Subsignal("ras_n", Pins("L21"), IOStandard("SSTL15")),
Subsignal("cas_n", Pins("L22"), IOStandard("SSTL15")),
Subsignal("we_n", Pins("K19"), IOStandard("SSTL15")),
#Subsignal("cs_n", Pins(""), IOStandard("SSTL15")), # Pulled low.
#Subsignal("dm", Pins(""), IOStandard("SSTL15")), # Pulled low.
Subsignal("dq", Pins(
" T21 U21 T22 U22 W20 W21 U20 V20",
"AA22 AB22 AA21 AB21 AB19 AB20 Y19 AA19",
" W16 Y16 U17 V17 AA17 AB17 AA16 AB16",
" V14 V13 W13 Y14 AA14 Y13 AA13 AB14"),
IOStandard("SSTL135"),
IOStandard("SSTL15"),
Misc("IN_TERM=UNTUNED_SPLIT_40")),
Subsignal("dqs_p", Pins("V22 Y20 U15 W15"),
IOStandard("DIFF_SSTL135"),
IOStandard("DIFF_SSTL15"),
Misc("IN_TERM=UNTUNED_SPLIT_40")),
Subsignal("dqs_n", Pins("W22 Y21 U16 Y15"),
IOStandard("DIFF_SSTL135"),
IOStandard("DIFF_SSTL15"),
Misc("IN_TERM=UNTUNED_SPLIT_40")),
Subsignal("clk_p", Pins("T16"), IOStandard("DIFF_SSTL135")),
Subsignal("clk_n", Pins("T17"), IOStandard("DIFF_SSTL135")),
Subsignal("cke", Pins("M21"), IOStandard("SSTL135")),
Subsignal("odt", Pins("M22"), IOStandard("SSTL135")),
Subsignal("reset_n", Pins("V18"), IOStandard("SSTL135")),
Subsignal("clk_p", Pins("T16"), IOStandard("DIFF_SSTL15")),
Subsignal("clk_n", Pins("T17"), IOStandard("DIFF_SSTL15")),
Subsignal("cke", Pins("M21"), IOStandard("SSTL15")),
Subsignal("odt", Pins("M22"), IOStandard("SSTL15")),
Subsignal("reset_n", Pins("V18"), IOStandard("SSTL15")),
Misc("SLEW=FAST"),
),
]
@ -109,6 +109,8 @@ _connectors = []
class Platform(XilinxPlatform):
def __init__(self):
XilinxPlatform.__init__(self, "xc7z020-clg484-1", _io, _connectors, toolchain="vivado")
self.add_platform_command("set_property INTERNAL_VREF 0.750 [get_iobanks 33]")
self.add_platform_command("set_property INTERNAL_VREF 0.750 [get_iobanks 34]")
def create_programmer(self):
return VivadoProgrammer()