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efinix_trion_t120_bga576_dev_kit: Enable target1 port and also connect it to SoC.
This commit is contained in:
Florent Kermarrec
parent
7ce6c4cf79
commit
996f5b2edd
1 changed files with 77 additions and 66 deletions
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@ -152,7 +152,7 @@ calc_result = design.auto_calc_pll_clock("dram_pll", {"CLKOUT0_FREQ": "400.0"})
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cs_dram_density = "8G",
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cs_speedbin = "800",
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target0_enable = "true",
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target1_enable = "false",
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target1_enable = "true",
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ctrl_type = "none"
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)
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@ -256,76 +256,87 @@ calc_result = design.auto_calc_pll_clock("dram_pll", {"CLKOUT0_FREQ": "400.0"})
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dram_pll_rst_n = platform.add_iface_io("dram_pll_rst_n")
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self.comb += dram_pll_rst_n.eq(platform.request("user_btn", 1))
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# DRAM AXI-Port.
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# DRAM AXI-Ports.
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# --------------
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axi_port = axi.AXIInterface(data_width=256, address_width=28, id_width=8) # 256MB.
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ios = [("axi0", 0,
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Subsignal("wdata", Pins(256)),
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Subsignal("wready", Pins(1)),
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Subsignal("wid", Pins(8)),
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Subsignal("bready", Pins(1)),
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Subsignal("rdata", Pins(256)),
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Subsignal("aid", Pins(8)),
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Subsignal("bvalid", Pins(1)),
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Subsignal("rlast", Pins(1)),
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Subsignal("bid", Pins(8)),
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Subsignal("asize", Pins(3)),
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Subsignal("atype", Pins(1)),
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Subsignal("aburst", Pins(2)),
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Subsignal("wvalid", Pins(1)),
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Subsignal("aaddr", Pins(32)),
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Subsignal("rid", Pins(8)),
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Subsignal("avalid", Pins(1)),
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Subsignal("rvalid", Pins(1)),
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Subsignal("alock", Pins(2)),
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Subsignal("rready", Pins(1)),
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Subsignal("rresp", Pins(2)),
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Subsignal("wstrb", Pins(32)),
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Subsignal("aready", Pins(1)),
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Subsignal("alen", Pins(8)),
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Subsignal("wlast", Pins(1)),
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)]
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io = platform.add_iface_ios(ios)
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rw_n = axi_port.ar.valid
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self.comb += [
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# Pseudo AW/AR Channels.
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io.atype.eq(~rw_n),
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io.aaddr.eq( Mux(rw_n, axi_port.ar.addr, axi_port.aw.addr)),
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io.aid.eq( Mux(rw_n, axi_port.ar.id, axi_port.aw.id)),
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io.alen.eq( Mux(rw_n, axi_port.ar.len, axi_port.aw.len)),
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io.asize.eq( Mux(rw_n, axi_port.ar.size, axi_port.aw.size)),
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io.aburst.eq( Mux(rw_n, axi_port.ar.burst, axi_port.aw.burst)),
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io.alock.eq( Mux(rw_n, axi_port.ar.lock, axi_port.aw.lock)),
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io.avalid.eq( Mux(rw_n, axi_port.ar.valid, axi_port.aw.valid)),
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axi_port.aw.ready.eq(~rw_n & io.aready),
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axi_port.ar.ready.eq( rw_n & io.aready),
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for n, data_width in {
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0: 256, # target0: 256-bit.
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1: 128, # target1: 128-bit
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}.items():
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axi_port = axi.AXIInterface(data_width=data_width, address_width=28, id_width=8) # 256MB.
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ios = [(f"axi{n}", 0,
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Subsignal("wdata", Pins(data_width)),
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Subsignal("wready", Pins(1)),
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Subsignal("wid", Pins(8)),
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Subsignal("bready", Pins(1)),
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Subsignal("rdata", Pins(data_width)),
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Subsignal("aid", Pins(8)),
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Subsignal("bvalid", Pins(1)),
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Subsignal("rlast", Pins(1)),
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Subsignal("bid", Pins(8)),
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Subsignal("asize", Pins(3)),
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Subsignal("atype", Pins(1)),
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Subsignal("aburst", Pins(2)),
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Subsignal("wvalid", Pins(1)),
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Subsignal("aaddr", Pins(32)),
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Subsignal("rid", Pins(8)),
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Subsignal("avalid", Pins(1)),
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Subsignal("rvalid", Pins(1)),
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Subsignal("alock", Pins(2)),
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Subsignal("rready", Pins(1)),
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Subsignal("rresp", Pins(2)),
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Subsignal("wstrb", Pins(data_width//8)),
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Subsignal("aready", Pins(1)),
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Subsignal("alen", Pins(8)),
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Subsignal("wlast", Pins(1)),
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)]
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io = platform.add_iface_ios(ios)
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rw_n = axi_port.ar.valid
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self.comb += [
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# Pseudo AW/AR Channels.
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io.atype.eq(~rw_n),
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io.aaddr.eq( Mux(rw_n, axi_port.ar.addr, axi_port.aw.addr)),
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io.aid.eq( Mux(rw_n, axi_port.ar.id, axi_port.aw.id)),
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io.alen.eq( Mux(rw_n, axi_port.ar.len, axi_port.aw.len)),
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io.asize.eq( Mux(rw_n, axi_port.ar.size, axi_port.aw.size)),
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io.aburst.eq( Mux(rw_n, axi_port.ar.burst, axi_port.aw.burst)),
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io.alock.eq( Mux(rw_n, axi_port.ar.lock, axi_port.aw.lock)),
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io.avalid.eq( Mux(rw_n, axi_port.ar.valid, axi_port.aw.valid)),
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axi_port.aw.ready.eq(~rw_n & io.aready),
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axi_port.ar.ready.eq( rw_n & io.aready),
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# R Channel.
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axi_port.r.id.eq(io.rid),
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axi_port.r.data.eq(io.rdata),
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axi_port.r.last.eq(io.rlast),
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axi_port.r.resp.eq(io.rresp),
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axi_port.r.valid.eq(io.rvalid),
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io.rready.eq(axi_port.r.ready),
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# R Channel.
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axi_port.r.id.eq(io.rid),
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axi_port.r.data.eq(io.rdata),
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axi_port.r.last.eq(io.rlast),
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axi_port.r.resp.eq(io.rresp),
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axi_port.r.valid.eq(io.rvalid),
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io.rready.eq(axi_port.r.ready),
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# W Channel.
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io.wid.eq(axi_port.w.id),
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io.wstrb.eq(axi_port.w.strb),
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io.wdata.eq(axi_port.w.data),
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io.wlast.eq(axi_port.w.last),
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io.wvalid.eq(axi_port.w.valid),
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axi_port.w.ready.eq(io.wready),
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# W Channel.
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io.wid.eq(axi_port.w.id),
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io.wstrb.eq(axi_port.w.strb),
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io.wdata.eq(axi_port.w.data),
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io.wlast.eq(axi_port.w.last),
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io.wvalid.eq(axi_port.w.valid),
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axi_port.w.ready.eq(io.wready),
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# B Channel.
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axi_port.b.id.eq(io.bid),
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axi_port.b.valid.eq(io.bvalid),
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io.bready.eq(axi_port.b.ready),
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]
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# B Channel.
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axi_port.b.id.eq(io.bid),
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axi_port.b.valid.eq(io.bvalid),
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io.bready.eq(axi_port.b.ready),
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]
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# Connect AXI interface to the main bus of the SoC.
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axi_lite_port = axi.AXILiteInterface(data_width=256, address_width=28)
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self.submodules += axi.AXILite2AXI(axi_lite_port, axi_port)
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self.bus.add_slave("main_ram", axi_lite_port, SoCRegion(origin=0x4000_0000, size=0x1000_0000)) # 256MB.
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# Connect AXI interface to the main bus of the SoC.
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axi_lite_port = axi.AXILiteInterface(data_width=data_width, address_width=28)
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self.submodules += axi.AXILite2AXI(axi_lite_port, axi_port)
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self.bus.add_slave(f"target{n}", axi_lite_port, SoCRegion(origin=0x4000_0000 + 0x1000_0000*n, size=0x1000_0000)) # 256MB.
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# Use DRAM's target0 port as Main Ram -----------------------------------------------------
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self.bus.add_region("main_ram", SoCRegion(
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origin = 0x4000_0000,
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size = 0x1000_0000, # 256MB.
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linker = True)
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)
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# Build --------------------------------------------------------------------------------------------
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