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efinix_trion_t120_bga576_dev_kit: Enable target1 port and also connect it to SoC.

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This commit is contained in:
Florent Kermarrec 2021-11-16 18:12:42 +01:00
parent 7ce6c4cf79
commit 996f5b2edd
1 changed files with 77 additions and 66 deletions
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29
litex_boards/targets/efinix_trion_t120_bga576_dev_kit.py
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@ -152,7 +152,7 @@ calc_result = design.auto_calc_pll_clock("dram_pll", {"CLKOUT0_FREQ": "400.0"})
cs_dram_density = "8G",
cs_speedbin = "800",
target0_enable = "true",
target1_enable = "false",
target1_enable = "true",
ctrl_type = "none"
)
@ -256,15 +256,19 @@ calc_result = design.auto_calc_pll_clock("dram_pll", {"CLKOUT0_FREQ": "400.0"})
dram_pll_rst_n = platform.add_iface_io("dram_pll_rst_n")
self.comb += dram_pll_rst_n.eq(platform.request("user_btn", 1))
# DRAM AXI-Port.
# DRAM AXI-Ports.
# --------------
axi_port = axi.AXIInterface(data_width=256, address_width=28, id_width=8) # 256MB.
ios = [("axi0", 0,
Subsignal("wdata", Pins(256)),
for n, data_width in {
0: 256, # target0: 256-bit.
1: 128, # target1: 128-bit
}.items():
axi_port = axi.AXIInterface(data_width=data_width, address_width=28, id_width=8) # 256MB.
ios = [(f"axi{n}", 0,
Subsignal("wdata", Pins(data_width)),
Subsignal("wready", Pins(1)),
Subsignal("wid", Pins(8)),
Subsignal("bready", Pins(1)),
Subsignal("rdata", Pins(256)),
Subsignal("rdata", Pins(data_width)),
Subsignal("aid", Pins(8)),
Subsignal("bvalid", Pins(1)),
Subsignal("rlast", Pins(1)),
@ -280,7 +284,7 @@ calc_result = design.auto_calc_pll_clock("dram_pll", {"CLKOUT0_FREQ": "400.0"})
Subsignal("alock", Pins(2)),
Subsignal("rready", Pins(1)),
Subsignal("rresp", Pins(2)),
Subsignal("wstrb", Pins(32)),
Subsignal("wstrb", Pins(data_width//8)),
Subsignal("aready", Pins(1)),
Subsignal("alen", Pins(8)),
Subsignal("wlast", Pins(1)),
@ -323,9 +327,16 @@ calc_result = design.auto_calc_pll_clock("dram_pll", {"CLKOUT0_FREQ": "400.0"})
]
# Connect AXI interface to the main bus of the SoC.
axi_lite_port = axi.AXILiteInterface(data_width=256, address_width=28)
axi_lite_port = axi.AXILiteInterface(data_width=data_width, address_width=28)
self.submodules += axi.AXILite2AXI(axi_lite_port, axi_port)
self.bus.add_slave("main_ram", axi_lite_port, SoCRegion(origin=0x4000_0000, size=0x1000_0000)) # 256MB.
self.bus.add_slave(f"target{n}", axi_lite_port, SoCRegion(origin=0x4000_0000 + 0x1000_0000*n, size=0x1000_0000)) # 256MB.
# Use DRAM's target0 port as Main Ram -----------------------------------------------------
self.bus.add_region("main_ram", SoCRegion(
origin = 0x4000_0000,
size = 0x1000_0000, # 256MB.
linker = True)
)
# Build --------------------------------------------------------------------------------------------