xilinx_alveo_u280: Switch HBM2 to USPHBM2 now integrated in LiteX.
This commit is contained in:
Florent Kermarrec
parent
b80c7a7843
commit
99a66274c8
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@ -25,6 +25,7 @@ from litex.soc.integration.soc import SoCRegion
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from litex.soc.integration.builder import *
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from litex.soc.interconnect.axi import *
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from litex.soc.interconnect.csr import *
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from litex.soc.cores.ram.xilinx_usp_hbm2 import USPHBM2
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from litex.soc.cores.led import LedChaser
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from litedram.modules import MTA18ASF2G72PZ
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@ -38,119 +39,6 @@ from litedram.frontend.axi import *
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from litescope import LiteScopeAnalyzer
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# HBM IP
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class HBMIP(Module, AutoCSR):
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"""Xilinx Virtex US+ High Bandwidth Memory 2 IP wrapper"""
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def __init__(self, platform, hbm_ip_name="hbm_0"):
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self.platform = platform
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self.hbm_name = hbm_ip_name
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self.axi = []
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self.apb = []
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self.hbm_params = {}
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self.init_done = CSRStatus()
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# # #
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class Open(Signal): pass
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# Clocks -----------------------------------------------------------------------------------
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# Ref = 100 MHz (HBM: 900 (225-900) MHz), drives internal PLL (1 per stack).
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for i in range(2):
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self.hbm_params[f"i_HBM_REF_CLK_{i:1d}"] = ClockSignal("hbm_ref")
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# APB: 100 (50-100) MHz
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for i in range(2):
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self.hbm_params[f"i_APB_{i:1d}_PCLK"] = ClockSignal("apb")
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self.hbm_params[f"i_APB_{i:1d}_PRESET_N"] = ~ResetSignal("apb")
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# AXI: 450 (225-450) MHz
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for i in range(32):
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self.hbm_params[f"i_AXI_{i:02d}_ACLK"] = ClockSignal("axi")
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self.hbm_params[f"i_AXI_{i:02d}_ARESET_N"] = ~ResetSignal("apb")
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# AXI --------------------------------------------------------------------------------------
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for i in range(32):
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axi = AXIInterface(data_width=256, address_width=33, id_width=6)
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self.axi.append(axi)
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# AW Channel.
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self.hbm_params[f"i_AXI_{i :02d}_AWADDR"] = axi.aw.addr
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self.hbm_params[f"i_AXI_{i :02d}_AWBURST"] = axi.aw.burst
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self.hbm_params[f"i_AXI_{i :02d}_AWID"] = axi.aw.id
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self.hbm_params[f"i_AXI_{i :02d}_AWLEN"] = axi.aw.len
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self.hbm_params[f"i_AXI_{i :02d}_AWSIZE"] = axi.aw.size
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self.hbm_params[f"i_AXI_{i :02d}_AWVALID"] = axi.aw.valid
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self.hbm_params[f"o_AXI_{i :02d}_AWREADY"] = axi.aw.ready
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# W Channel.
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self.hbm_params[f"i_AXI_{i:02d}_WDATA"] = axi.w.data
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self.hbm_params[f"i_AXI_{i:02d}_WLAST"] = axi.w.last
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self.hbm_params[f"i_AXI_{i:02d}_WSTRB"] = axi.w.strb
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self.hbm_params[f"i_AXI_{i:02d}_WDATA_PARITY"] = 0 # FIXME: Manage parity?
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self.hbm_params[f"i_AXI_{i:02d}_WVALID"] = axi.w.valid
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self.hbm_params[f"o_AXI_{i:02d}_WREADY"] = axi.w.ready
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# B Channel.
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self.hbm_params[f"o_AXI_{i:02d}_BID"] = axi.b.id
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self.hbm_params[f"o_AXI_{i:02d}_BRESP"] = axi.b.resp
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self.hbm_params[f"o_AXI_{i:02d}_BVALID"] = axi.b.valid
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self.hbm_params[f"i_AXI_{i:02d}_BREADY"] = axi.b.ready
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# AR Channel.
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self.hbm_params[f"i_AXI_{i:02d}_ARADDR"] = axi.ar.addr
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self.hbm_params[f"i_AXI_{i:02d}_ARBURST"] = axi.ar.burst
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self.hbm_params[f"i_AXI_{i:02d}_ARID"] = axi.ar.id
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self.hbm_params[f"i_AXI_{i:02d}_ARLEN"] = axi.ar.len
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self.hbm_params[f"i_AXI_{i:02d}_ARSIZE"] = axi.ar.size
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self.hbm_params[f"i_AXI_{i:02d}_ARVALID"] = axi.ar.valid
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self.hbm_params[f"o_AXI_{i:02d}_ARREADY"] = axi.ar.ready
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# R Channel.
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self.hbm_params[f"o_AXI_{i:02d}_RDATA_PARITY"] = Open() # FIXME: Manage parity?
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self.hbm_params[f"o_AXI_{i:02d}_RDATA"] = axi.r.data
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self.hbm_params[f"o_AXI_{i:02d}_RID"] = axi.r.id
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self.hbm_params[f"o_AXI_{i:02d}_RLAST"] = axi.r.last
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self.hbm_params[f"o_AXI_{i:02d}_RRESP"] = axi.r.resp
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self.hbm_params[f"o_AXI_{i:02d}_RVALID"] = axi.r.valid
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self.hbm_params[f"i_AXI_{i:02d}_RREADY"] = axi.r.ready
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# APB --------------------------------------------------------------------------------------
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# FIXME: Connect to CSR or Wishbone.
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apb_complete = Signal(2)
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for i in range(2):
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self.hbm_params[f"i_APB_{i:1d}_PWDATA"] = 0
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self.hbm_params[f"i_APB_{i:1d}_PADDR"] = 0
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self.hbm_params[f"i_APB_{i:1d}_PENABLE"] = 0
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self.hbm_params[f"i_APB_{i:1d}_PSEL"] = 0
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self.hbm_params[f"i_APB_{i:1d}_PWRITE"] = 0
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self.hbm_params[f"o_APB_{i:1d}_PRDATA"] = Open()
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self.hbm_params[f"o_APB_{i:1d}_PREADY"] = Open()
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self.hbm_params[f"o_APB_{i:1d}_PSLVERR"] = Open()
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self.hbm_params[f"o_apb_complete_{i:1d}"] = apb_complete[i]
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self.comb += self.init_done.status.eq(apb_complete == 0b11)
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# Temperature ------------------------------------------------------------------------------
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for i in range(2):
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self.hbm_params[f"o_DRAM_{i:1d}_STAT_CATTRIP"] = Open()
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self.hbm_params[f"o_DRAM_{i:1d}_STAT_TEMP"] = Open()
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def add_sources(self, platform):
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this_dir = os.path.dirname(os.path.abspath(os.path.realpath(__file__)))
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os.system("wget https://github.com/litex-hub/litex-boards/files/6893157/hbm_0.xci.txt")
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os.makedirs("ip/hbm", exist_ok=True)
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os.system("mv hbm_0.xci.txt ip/hbm/hbm_0.xci")
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platform.add_ip(os.path.join(this_dir, "ip", "hbm", self.hbm_name + ".xci"))
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def do_finalize(self):
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self.add_sources(self.platform)
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self.specials += Instance(self.hbm_name, **self.hbm_params)
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# CRG ----------------------------------------------------------------------------------------------
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class _CRG(Module):
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@ -215,7 +103,12 @@ class BaseSoC(SoCCore):
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#self.add_jtagbone(chain=2) # Chain 1 already used by HBM2 debug probes.
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# Add HBM Core.
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self.submodules.hbm = hbm = ClockDomainsRenamer({"axi": "sys"})(HBMIP(platform))
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self.submodules.hbm = hbm = ClockDomainsRenamer({"axi": "sys"})(USPHBM2(platform))
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# Get HBM .xci.
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os.system("wget https://github.com/litex-hub/litex-boards/files/6893157/hbm_0.xci.txt")
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os.makedirs("ip/hbm", exist_ok=True)
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os.system("mv hbm_0.xci.txt ip/hbm/hbm_0.xci")
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# Connect four of the HBM's AXI interfaces to the main bus of the SoC.
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for i in range(4):
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