Merge pull request #575 from trabucayre/xilinx_zc706
xilinx_zc706: new Xilinx/AMD Zynq7000 based board
This commit is contained in:
enjoy-digital
GitHub
commit
99c05f7050
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@ -256,6 +256,7 @@ Some of the suported boards, see yours? Give LiteX-Boards a try!
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├── xilinx_sp605
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├── xilinx_vc707
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├── xilinx_vcu118
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├── xilinx_zc706
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├── xilinx_zcu102
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├── xilinx_zcu104
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├── xilinx_zcu106
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@ -0,0 +1,337 @@
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#
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# This file is part of LiteX-Boards.
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#
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# Copyright (c) 2024 Gwenhael Goavec-Merou <gwenhael@enjoy-digital.fr>
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# SPDX-License-Identifier: BSD-2-Clause
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from litex.build.generic_platform import *
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from litex.build.xilinx import Xilinx7SeriesPlatform
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from litex.build.openfpgaloader import OpenFPGALoader
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# IOs ----------------------------------------------------------------------------------------------
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_io = [
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# Clk / Rst.
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("sysclk", 0,
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Subsignal("p", Pins("H9"), IOStandard("LVDS")),
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Subsignal("n", Pins("G9"), IOStandard("LVDS")),
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),
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("usrclk", 0,
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Subsignal("p", Pins("AF14"), IOStandard("LVDS_25")),
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Subsignal("n", Pins("AG14"), IOStandard("LVDS_25")),
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),
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("cpu_reset", 0, Pins("A8"), IOStandard("LVCMOS15")),
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# Leds.
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("user_led", 0, Pins("Y21"), IOStandard("LVCMOS25")),
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("user_led", 1, Pins("G2"), IOStandard("LVCMOS15")),
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("user_led", 2, Pins("W21"), IOStandard("LVCMOS25")),
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("user_led", 3, Pins("A17"), IOStandard("LVCMOS15")),
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# Buttons.
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("user_btn_l", 0, Pins("AK25"), IOStandard("LVCMOS25")),
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("user_btn_c", 0, Pins("K15"), IOStandard("LVCMOS15")),
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("user_btn_r", 0, Pins("R27"), IOStandard("LVCMOS25")),
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# Switches.
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("user_dip_btn", 3, Pins("AJ13"), IOStandard("LVCMOS25")),
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("user_dip_btn", 2, Pins("AC17"), IOStandard("LVCMOS25")),
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("user_dip_btn", 1, Pins("AC16"), IOStandard("LVCMOS25")),
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("user_dip_btn", 0, Pins("AB17"), IOStandard("LVCMOS25")),
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# SMA.
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("user_sma_clock", 0,
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Subsignal("p", Pins("AD18"), IOStandard("LVDS_25"),
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Misc("DIFF_TERM=TRUE")),
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Subsignal("n", Pins("AD19"), IOStandard("LVDS_25"),
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Misc("DIFF_TERM=TRUE")),
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),
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("user_sma_clock_p", Pins("AD18"), IOStandard("LVCMOS25")),
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("user_sma_clock_n", Pins("AD19"), IOStandard("LVCMOS25")),
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# PCIe.
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("pcie_x1", 0,
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Subsignal("rst_n", Pins("AK23"), IOStandard("LVCMOS25")),
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Subsignal("wake_n", Pins("AK22"), IOStandard("LVCMOS25")),
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Subsignal("clk_p", Pins("N8")),
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Subsignal("clk_n", Pins("N7")),
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Subsignal("tx_p", Pins("N4")),
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Subsignal("tx_n", Pins("N3")),
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Subsignal("rx_p", Pins("P6")),
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Subsignal("rx_n", Pins("P5")),
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),
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("pcie_x2", 0,
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Subsignal("rst_n", Pins("AK23"), IOStandard("LVCMOS25")),
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Subsignal("wake_n", Pins("AK22"), IOStandard("LVCMOS25")),
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Subsignal("clk_p", Pins("N8")),
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Subsignal("clk_n", Pins("N7")),
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Subsignal("tx_p", Pins("N4 P2")),
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Subsignal("tx_n", Pins("N3 P1")),
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Subsignal("rx_p", Pins("P6 T6")),
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Subsignal("rx_n", Pins("P5 T5")),
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),
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("pcie_x4", 0,
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Subsignal("rst_n", Pins("AK23"), IOStandard("LVCMOS25")),
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Subsignal("wake_n", Pins("AK22"), IOStandard("LVCMOS25")),
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Subsignal("clk_p", Pins("N8")),
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Subsignal("clk_n", Pins("N7")),
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Subsignal("tx_p", Pins("N4 P2 R4 T2")),
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Subsignal("tx_n", Pins("N3 P1 R3 T1")),
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Subsignal("rx_p", Pins("P6 T6 U4 V6")),
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Subsignal("rx_n", Pins("P5 T5 U3 V5")),
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),
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# SFP.
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("sfp", 0,
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Subsignal("txp", Pins("W4")),
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Subsignal("txn", Pins("W3")),
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Subsignal("rxp", Pins("Y6")),
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Subsignal("rxn", Pins("Y5")),
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),
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("sfp_tx", 0,
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Subsignal("p", Pins("W4")),
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Subsignal("n", Pins("W3")),
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),
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("sfp_rx", 0,
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Subsignal("p", Pins("Y6")),
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Subsignal("n", Pins("Y5")),
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),
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("sfp_tx_disable_n", 0, Pins("AA18"), IOStandard("LVCMOS25")),
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]
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# Connectors ---------------------------------------------------------------------------------------
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_connectors = [
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("pmod1", "AJ21 AK21 AB21 AB16 Y20 AA20 AC18 AC19"),
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("HPC", {
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# A
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"DP1_M2C_P" : "AJ8",
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"DP1_M2C_N" : "AJ7",
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"DP2_M2C_P" : "AG8",
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"DP2_M2C_N" : "AG7",
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"DP3_M2C_P" : "AE8",
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"DP3_M2C_N" : "AE7",
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"DP4_M2C_P" : "AH6",
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"DP4_M2C_N" : "AH5",
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"DP5_M2C_P" : "AG4",
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"DP5_M2C_N" : "AG3",
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"DP1_C2M_P" : "AK6",
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"DP1_C2M_N" : "AK5",
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"DP2_C2M_P" : "AJ4",
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"DP2_C2M_N" : "AJ3",
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"DP3_C2M_P" : "AK2",
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"DP3_C2M_N" : "AK1",
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"DP4_C2M_P" : "AH2",
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"DP4_C2M_N" : "AH1",
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"DP5_C2M_P" : "AF2",
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"DP5_C2M_N" : "AF1",
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# B
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"DP7_M2C_P" : "AD6",
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"DP7_M2C_N" : "AD5",
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"DP6_M2C_P" : "AF6",
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"DP6_M2C_N" : "AF5",
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"GBTCLK1_M2C_C_P" : "AA8",
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"GBTCLK1_M2C_C_N" : "AA7",
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"DP7_C2M_P" : "AD2",
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"DP7_C2M_N" : "AD1",
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"DP6_C2M_P" : "AE4",
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"DP6_C2M_N" : "AE3",
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# C
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"DP0_C2M_P" : "AK10",
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"DP0_C2M_N" : "AK9",
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"DP0_M2C_P" : "AH10",
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"DP0_M2C_N" : "AH9",
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"LA06_P" : "AG22",
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"LA06_N" : "AH22",
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"LA10_P" : "AG24",
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"LA10_N" : "AG25",
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"LA14_P" : "AC24",
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"LA14_N" : "AD24",
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"LA18_CC_P" : "W25",
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"LA18_CC_N" : "W26",
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"LA27_P" : "V28",
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"LA27_N" : "V29",
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# C
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"GBTCLK0_M2C_C_P" : "AD10",
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"GBTCLK0_M2C_C_N" : "AD9",
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"LA01_CC_P" : "AG21",
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"LA01_CC_N" : "AH21",
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"LA05_P" : "AH23",
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"LA05_N" : "AH24",
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"LA09_P" : "AD21",
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"LA09_N" : "AE21",
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"LA13_P" : "AA22",
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"LA13_N" : "AA23",
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"LA17_CC_P" : "V23",
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"LA17_CC_N" : "W24",
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"LA23_P" : "P25",
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"LA23_N" : "P26",
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"LA26_P" : "R28",
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"LA26_N" : "T28",
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# G
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"CLK1_M2C_P" : "U26",
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"CLK1_M2C_N" : "U27",
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"LA00_CC_P" : "AF20",
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"LA00_CC_N" : "AG20",
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"LA03_P" : "AH19",
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"LA03_N" : "AJ19",
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"LA08_P" : "AF19",
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"LA08_N" : "AG19",
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"LA12_P" : "AF23",
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"LA12_N" : "AF24",
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"LA16_P" : "AA24",
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"LA16_N" : "AB24",
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"LA20_P" : "U25",
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"LA20_N" : "V26",
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"LA22_P" : "V27",
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"LA22_N" : "W28",
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"LA25_P" : "T29",
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"LA25_N" : "U29",
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"LA29_P" : "R25",
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"LA29_N" : "R26",
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"LA31_P" : "N29",
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"LA31_N" : "P29",
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"LA33_P" : "N26",
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"LA33_N" : "N27",
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# H
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"CLK0_M2C_P" : "AE22",
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"CLK0_M2C_N" : "AF22",
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"LA02_P" : "AK17",
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"LA02_N" : "AK18",
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"LA04_P" : "AJ20",
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"LA04_N" : "AK20",
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"LA07_P" : "AJ23",
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"LA07_N" : "AJ24",
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"LA11_P" : "AD23",
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"LA11_N" : "AE23",
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"LA15_P" : "Y22",
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"LA15_N" : "Y23",
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"LA19_P" : "T24",
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"LA19_N" : "T25",
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"LA21_P" : "W29",
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"LA21_N" : "W30",
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"LA24_P" : "T30",
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"LA24_N" : "U30",
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"LA28_P" : "P30",
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"LA28_N" : "R30",
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"LA30_P" : "P23",
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"LA30_N" : "P24",
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"LA32_P" : "P21",
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"LA32_N" : "R21",
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}
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),
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("LPC", {
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# C
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"DP0_C2M_P" : "AB2",
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"DP0_C2M_N" : "AB1",
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"DP0_M2C_P" : "AC4",
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"DP0_M2C_N" : "AC3",
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"LA06_P" : "AB12",
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"LA06_N" : "AC12",
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"LA10_P" : "AC14",
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"LA10_N" : "AC13",
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"LA14_P" : "AF18",
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"LA14_N" : "AF17",
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"LA18_CC_P" : "AE27",
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"LA18_CC_N" : "AF27",
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"LA27_P" : "AJ28",
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"LA27_N" : "AJ29",
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# D
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"GBTCLK0_M2C_C_P" : "U8",
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"GBTCLK0_M2C_C_N" : "U7",
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"LA01_CC_P" : "AF15",
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"LA01_CC_N" : "AG15",
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"LA05_P" : "AE16",
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"LA05_N" : "AE15",
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"LA09_P" : "AH14",
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"LA09_N" : "AH13",
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"LA13_P" : "AH17",
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"LA13_N" : "AH16",
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"LA17_CC_P" : "AB27",
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"LA17_CC_N" : "AC27",
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"LA23_P" : "AJ26",
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"LA23_N" : "AK26",
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"LA26_P" : "AJ30",
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"LA26_N" : "AK30",
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# G
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"CLK1_M2C_P" : "AC28",
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"CLK1_M2C_N" : "AD28",
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"LA00_CC_P" : "AE13",
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"LA00_CC_N" : "AF13",
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"LA03_P" : "AG12",
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"LA03_N" : "AH12",
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"LA08_P" : "AD14",
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"LA08_N" : "AD13",
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"LA12_P" : "AD16",
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"LA12_N" : "AD15",
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"LA16_P" : "AE18",
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"LA16_N" : "AE17",
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"LA20_P" : "AG26",
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"LA20_N" : "AG27",
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"LA22_P" : "AK27",
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"LA22_N" : "AK28",
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"LA25_P" : "AF29",
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"LA25_N" : "AG29",
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"LA29_P" : "AE25",
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"LA29_N" : "AF25",
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"LA31_P" : "AC29",
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"LA31_N" : "AD29",
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"LA33_P" : "Y30",
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"LA33_N" : "AA30",
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# H
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"CLK0_M2C_P" : "AG17",
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"CLK0_M2C_N" : "AG16",
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"LA02_P" : "AE12",
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"LA02_N" : "AF12",
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"LA04_P" : "AJ15",
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"LA04_N" : "AK15",
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"LA07_P" : "AA15",
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"LA07_N" : "AA14",
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"LA11_P" : "AJ16",
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"LA11_N" : "AK16",
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"LA15_P" : "AB15",
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"LA15_N" : "AB14",
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"LA19_P" : "AH26",
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"LA19_N" : "AH27",
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"LA21_P" : "AH28",
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"LA21_N" : "AH29",
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"LA24_P" : "AF30",
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"LA24_N" : "AG30",
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"LA28_P" : "AD25",
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"LA28_N" : "AE26",
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"LA30_P" : "AB29",
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"LA30_N" : "AB30",
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"LA32_P" : "Y26",
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"LA32_N" : "Y27",
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}
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),
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("XADC", {
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"AD1_R_N" : "K13",
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"AD1_R_P" : "L13",
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"GPIO_0" : "H14",
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"GPIO_1" : "J15",
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"GPIO_2" : "J16",
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"GPIO_3" : "J14",
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"VAUX0N_R" : "L14",
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"VAUX0P_R" : "L15",
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"VAUX8N_R" : "H13",
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"VAUX8P_R" : "J13",
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}
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),
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]
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# Platform -----------------------------------------------------------------------------------------
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class Platform(Xilinx7SeriesPlatform):
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default_clk_name = "sysclk"
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default_clk_period = 1e9/200e6
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def __init__(self, toolchain="vivado"):
|
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Xilinx7SeriesPlatform.__init__(self, "xc7z045ffg900-2", _io, _connectors, toolchain=toolchain)
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def create_programmer(self):
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return OpenFPGALoader("zc706")
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def do_finalize(self, fragment):
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Xilinx7SeriesPlatform.do_finalize(self, fragment)
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self.add_period_constraint(self.lookup_request("sysclk", loose=True), 1e9/200e6)
|
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|
|
@ -0,0 +1,5 @@
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source [find interface/ftdi/digilent_jtag_smt2.cfg]
|
||||
|
||||
reset_config srst_only srst_push_pull
|
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|
||||
source [find target/zynq_7000.cfg]
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|
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@ -0,0 +1,86 @@
|
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#!/usr/bin/env python3
|
||||
|
||||
#
|
||||
# This file is part of LiteX-Boards.
|
||||
#
|
||||
# Copyright (c) 2024 Gwenhael Goavec-Merou <gwenhael@enjoy-digital.fr>
|
||||
# SPDX-License-Identifier: BSD-2-Clause
|
||||
|
||||
# Build/use
|
||||
# Build/Load bitstream:
|
||||
# ./xilinx_zc706.py --with-jtagbone --uart-name=crossover --csr-csv=csr.csv --build --load
|
||||
#
|
||||
# litex_server --jtag --jtag-config openocd_xc7z_smt2-nc.cfg
|
||||
#
|
||||
# In a second terminal:
|
||||
# litex_cli --regs # to dump all registers
|
||||
# Or
|
||||
# litex_term crossover # to have access to LiteX bios
|
||||
#
|
||||
# --------------------------------------------------------------------------------------------------
|
||||
|
||||
from migen import *
|
||||
|
||||
from litex.gen import *
|
||||
|
||||
from litex_boards.platforms import xilinx_zc706
|
||||
|
||||
from litex.soc.cores.clock import *
|
||||
from litex.soc.integration.soc_core import *
|
||||
from litex.soc.integration.builder import *
|
||||
from litex.soc.cores.led import LedChaser
|
||||
|
||||
# CRG ----------------------------------------------------------------------------------------------
|
||||
|
||||
class _CRG(LiteXModule):
|
||||
def __init__(self, platform, sys_clk_freq):
|
||||
self.rst = Signal()
|
||||
self.cd_sys = ClockDomain()
|
||||
|
||||
# # #
|
||||
|
||||
self.pll = pll = S7PLL(speedgrade=-1)
|
||||
self.comb += pll.reset.eq(self.rst)
|
||||
pll.register_clkin(platform.request("sysclk"), 200e6)
|
||||
pll.create_clkout(self.cd_sys, sys_clk_freq)
|
||||
platform.add_false_path_constraints(self.cd_sys.clk, pll.clkin) # Ignore sys_clk to pll.clkin path created by SoC's rst.
|
||||
|
||||
# BaseSoC ------------------------------------------------------------------------------------------
|
||||
|
||||
class BaseSoC(SoCCore):
|
||||
def __init__(self, sys_clk_freq=100e6, with_led_chaser=True, **kwargs):
|
||||
platform = xilinx_zc706.Platform()
|
||||
kwargs["uart_name"] = "crossover"
|
||||
kwargs["with_jtagbone"] = True
|
||||
|
||||
# CRG --------------------------------------------------------------------------------------
|
||||
self.crg = _CRG(platform, sys_clk_freq)
|
||||
|
||||
# SoCCore ----------------------------------------------------------------------------------
|
||||
SoCCore.__init__(self, platform, sys_clk_freq, ident="LiteX SoC on ZCU102", **kwargs)
|
||||
|
||||
# Leds -------------------------------------------------------------------------------------
|
||||
if with_led_chaser:
|
||||
self.leds = LedChaser(
|
||||
pads = platform.request_all("user_led"),
|
||||
sys_clk_freq = sys_clk_freq
|
||||
)
|
||||
|
||||
# Build --------------------------------------------------------------------------------------------
|
||||
def main():
|
||||
from litex.build.parser import LiteXArgumentParser
|
||||
parser = LiteXArgumentParser(platform=xilinx_zc706.Platform, description="LiteX SoC on ZC706.")
|
||||
parser.add_target_argument("--sys-clk-freq", default=100e6, type=float, help="System clock generator.")
|
||||
args = parser.parse_args()
|
||||
|
||||
soc = BaseSoC(sys_clk_freq=args.sys_clk_freq, **parser.soc_argdict)
|
||||
builder = Builder(soc, **parser.builder_argdict)
|
||||
if args.build:
|
||||
builder.build(**parser.toolchain_argdict)
|
||||
|
||||
if args.load:
|
||||
prog = soc.platform.create_programmer()
|
||||
prog.load_bitstream(builder.get_bitstream_filename(mode="sram"))
|
||||
|
||||
if __name__ == "__main__":
|
||||
main()
|
||||
Loading…
Reference in New Issue