sipeed_tang_primer_25k: new board
This commit is contained in:
Gwenhael Goavec-Merou
parent
3a75f6cf79
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#
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# This file is part of LiteX-Boards.
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#
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# Copyright (c) 2023 Gwenhael Goavec-Merou <gwenhael.goavec-merou@trabucayre.com>
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# SPDX-License-Identifier: BSD-2-Clause
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from migen import *
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from litex.build.generic_platform import *
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from litex.build.gowin.platform import GowinPlatform
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from litex.build.openfpgaloader import OpenFPGALoader
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# IOs ----------------------------------------------------------------------------------------------
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_io = [
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# Clk / Rst.
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("clk50", 0, Pins("E2"), IOStandard("LVCMOS33")),
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# SPIFlash.
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("spiflash", 0,
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Subsignal("cs_n", Pins("E6"), IOStandard("LVCMOS33")),
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Subsignal("clk", Pins("E7"), IOStandard("LVCMOS33")),
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Subsignal("mosi", Pins("D6"), IOStandard("LVCMOS33")),
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Subsignal("miso", Pins("E5"), IOStandard("LVCMOS33")),
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Subsignal("wp", Pins("D5"), IOStandard("LVCMOS33")),
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Subsignal("hold", Pins("E4"), IOStandard("LVCMOS33")),
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),
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("spiflashx4", 0,
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Subsignal("cs_n", Pins("E6"), IOStandard("LVCMOS33")),
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Subsignal("clk", Pins("E7"), IOStandard("LVCMOS33")),
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Subsignal("dq", Pins("D6 E5 D5 E4"), IOStandard("LVCMOS33")),
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),
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]
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# Dock 204 Pins SODIMM Connector -------------------------------------------------------------------
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_connectors = [
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["J1",
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# -------------------------------------------------
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"---", # 0
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# GND GND ( 1-10).
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" --- --- L9 H5 K9 J5 J8 L5 K8 K5",
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# GND (11-20).
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" F7 H8 F6 H7 --- G7 E8 G8 B3 F5",
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# 3V3 3V3 GND GND 3V3 (21-30).
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" C3 G5 E3 --- D7 --- --- --- --- L6",
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# 3V3 (31-40).
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" --- K6 J11 K7 J10 J7 H11 L7 H10 L8",
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# GND GND (41-50).
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" G11 L10 G10 K10 --- K11 D11 L11 D10 ---",
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# GND GND (51-60).
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" C11 E11 C10 E10 B11 A11 B10 A10 --- ---",
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],
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["J2",
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# ----------------------------------------------------------------------
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"---", # 0
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# GND 3V3 3V3 ( 1-10).
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" --- --- B2 --- C2 L2 F2 L1 F1 K1",
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# GND (11-20).
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" A1 K2 D8 J4 E1 K4 D1 G2 --- G1",
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# TCK TMS TDO TDI GND (21-30).
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" C1 L4 B1 L3 A2 J1 A3 J2 --- G4",
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# GND 1V8 1V8 (31-40).
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" M0_D3_P H4 M0_D3_N H1 --- H2 M0_D2_P --- M0_D2_N ---",
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# GND 2V5 2V5 3V3 GND 3V3 3V3 (41-50).
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" --- --- M0_CK_P --- M0_CK_N --- --- --- M0_D1_P ---",
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# 5V GND GND 5V 5V GND 5V (51-60).
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" M0_D1_N --- --- --- M0_D0_P --- M0_D0_N --- --- ---",
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],
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]
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# Dock IOs -----------------------------------------------------------------------------------------
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_dock_io = [
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# Serial.
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("serial", 0,
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Subsignal("rx", Pins("J1:20")),
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Subsignal("tx", Pins("J1:19")),
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IOStandard("LVCMOS33")
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),
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# Leds.
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("led", 0, Pins("J1:17"), IOStandard("LVCMOS33")), # Pin READY.
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("led", 1, Pins("J1:25"), IOStandard("LVCMOS33")), # Pin DONE.
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# Buttons.
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("btn_n", 0, Pins("J1:37"), IOStandard("LVCMOS33")),
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("btn_n", 1, Pins("J1:39"), IOStandard("LVCMOS33")),
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# USB.
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("usb", 0,
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Subsignal("d_p", Pins("J1:30")),
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Subsignal("d_n", Pins("J1:32")),
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IOStandard("LVCMOS33"),
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),
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]
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_dock_connectors = [
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# Pmod
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("j4", "G11 D11 B11 C11 G10 D10 B10 C10"),
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("j5", "A11 E11 K11 L5 A10 E10 L11 K5"),
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("j6", " F5 G7 H8 H5 G5 G8 H7 J5"),
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("j3", {
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1: "K2", 2: "K1",
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3: "L1", 4: "L2",
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5: "K4", 6: "J4",
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7: "G1", 8: "G2",
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9: "L3", 10: "L4",
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11: "---", 12: "---",
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13: "C2", 14: "B2",
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15: "F1", 16: "F2",
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17: "A1", 18: "E1",
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19: "D1", 20: "E3",
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21: "J2", 22: "J1",
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23: "H4", 24: "G4",
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25: "H2", 26: "H1",
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27: "J7", 28: "K7",
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29: "L8", 30: "L7",
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31: "K10", 32: "L10",
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33: "K9", 34: "L9",
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35: "K8", 36: "J8",
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37: "F6", 38: "F7",
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39: "J10", 40: "J11",
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}),
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]
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# Platform -----------------------------------------------------------------------------------------
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class Platform(GowinPlatform):
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default_clk_name = "clk50"
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default_clk_period = 1e9/50e6
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def __init__(self, toolchain="gowin"):
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GowinPlatform.__init__(self, "GW5A-LV25MG121NC1/I0", _io, _connectors, toolchain=toolchain, devicename="GW5A-25A")
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self.add_extension(_dock_io)
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self.add_connector(_dock_connectors)
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self.toolchain.options["use_mspi_as_gpio"] = 1 # spi flash
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self.toolchain.options["use_ready_as_gpio"] = 1 # led
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self.toolchain.options["use_done_as_gpio"] = 1 # led
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self.toolchain.options["use_cpu_as_gpio"] = 1 # clk
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self.toolchain.options["rw_check_on_ram"] = 1
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def create_programmer(self, kit="openfpgaloader"):
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return OpenFPGALoader(cable="ft2232")
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def do_finalize(self, fragment):
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GowinPlatform.do_finalize(self, fragment)
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self.add_period_constraint(self.lookup_request("clk50", loose=True), 1e9/50e6)
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@ -0,0 +1,108 @@
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#!/usr/bin/env python3
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#
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# This file is part of LiteX-Boards.
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#
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# Copyright (c) 2023 Gwenhael Goavec-Merou <gwenhael.goavec-merou@trabucayre.com>
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# SPDX-License-Identifier: BSD-2-Clause
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from migen import *
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from litex.gen import *
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from litex.soc.cores.clock.gowin_gw5a import GW5APLL
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from litex.soc.integration.soc_core import *
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from litex.soc.integration.builder import *
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from litex.soc.cores.led import LedChaser
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from litex.soc.cores.gpio import GPIOIn
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from litex_boards.platforms import sipeed_tang_primer_25k
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# CRG ----------------------------------------------------------------------------------------------
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class _CRG(LiteXModule):
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def __init__(self, platform, sys_clk_freq):
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self.rst = Signal()
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self.cd_sys = ClockDomain()
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self.cd_por = ClockDomain()
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# # #
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# Clk
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clk50 = platform.request("clk50")
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# Power on reset
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por_count = Signal(16, reset=2**16-1)
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por_done = Signal()
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self.comb += [
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self.cd_por.clk.eq(clk50),
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por_done.eq(por_count == 0),
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]
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self.sync.por += If(~por_done, por_count.eq(por_count - 1))
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# PLL
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self.pll = pll = GW5APLL(devicename=platform.devicename, device=platform.device)
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self.comb += pll.reset.eq(~por_done | self.rst)
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pll.register_clkin(clk50, 50e6)
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pll.create_clkout(self.cd_sys, sys_clk_freq)
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# BaseSoC ------------------------------------------------------------------------------------------
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class BaseSoC(SoCCore):
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def __init__(self, sys_clk_freq=50e6,
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with_spi_flash = False,
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with_led_chaser = True,
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with_buttons = True,
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**kwargs):
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platform = sipeed_tang_primer_25k.Platform(toolchain="gowin")
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# CRG --------------------------------------------------------------------------------------
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self.crg = _CRG(platform, sys_clk_freq)
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# SoCCore ----------------------------------------------------------------------------------
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SoCCore.__init__(self, platform, sys_clk_freq, ident="LiteX SoC on Tang Primer 25K", **kwargs)
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# SPI Flash --------------------------------------------------------------------------------
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if with_spi_flash:
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from litespi.modules import W25Q64FV as SpiFlashModule
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from litespi.opcodes import SpiNorFlashOpCodes as Codes
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self.add_spi_flash(mode="1x", module=SpiFlashModule(Codes.READ_1_1_1))
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# Leds -------------------------------------------------------------------------------------
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if with_led_chaser:
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self.leds = LedChaser(
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pads = platform.request_all("led"),
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sys_clk_freq = sys_clk_freq
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)
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# Buttons ----------------------------------------------------------------------------------
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if with_buttons:
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self.buttons = GPIOIn(pads=~platform.request_all("btn_n"))
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# Build --------------------------------------------------------------------------------------------
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def main():
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from litex.build.parser import LiteXArgumentParser
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parser = LiteXArgumentParser(platform=sipeed_tang_primer_25k.Platform, description="LiteX SoC on Tang Primer 25K.")
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parser.add_target_argument("--flash", action="store_true", help="Flash Bitstream.")
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parser.add_target_argument("--sys-clk-freq", default=50e6, type=float, help="System clock frequency.")
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parser.add_target_argument("--with-spi-flash", action="store_true", help="Enable SPI Flash (MMAPed).")
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args = parser.parse_args()
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soc = BaseSoC(
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sys_clk_freq = args.sys_clk_freq,
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with_spi_flash = args.with_spi_flash,
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**parser.soc_argdict
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)
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builder = Builder(soc, **parser.builder_argdict)
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if args.build:
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builder.build(**parser.toolchain_argdict)
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if args.load:
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prog = soc.platform.create_programmer()
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prog.load_bitstream(builder.get_bitstream_filename(mode="sram"))
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if __name__ == "__main__":
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main()
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