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Merge pull request #80 from rob-ng15/master 

Use 128mb sdram, uart via i/o port on i/o board and vga terminal via i/o board
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enjoy-digital 2020-06-11 18:16:18 +02:00 committed by GitHub
parent 45bd50b000 485c242f24
commit 9aea2272eb
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2 changed files with 119 additions and 34 deletions
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64
litex_boards/platforms/de10nano.py
View File

@ -18,6 +18,8 @@ _io = [
("user_led", 3, Pins("V15"), IOStandard("3.3-V LVTTL")),
("user_led", 4, Pins("AF26"), IOStandard("3.3-V LVTTL")),
("user_led", 5, Pins("AE26"), IOStandard("3.3-V LVTTL")),
("user_led", 6, Pins("Y16"), IOStandard("3.3-V LVTTL")),
("user_led", 7, Pins("AA23"), IOStandard("3.3-V LVTTL")),
("key", 0, Pins("AH17"), IOStandard("3.3-V LVTTL")),
("key", 1, Pins("AH16"), IOStandard("3.3-V LVTTL")),
@ -27,11 +29,17 @@ _io = [
("user_sw", 2, Pins("W21"), IOStandard("3.3-V LVTTL")),
("user_sw", 3, Pins("W20"), IOStandard("3.3-V LVTTL")),
# uncomment appropriate serial for board
("serial", 0,
Subsignal("tx", Pins("AF13"), IOStandard("3.3-V LVTTL")), # Arduino_IO1
Subsignal("rx", Pins("AG13"), IOStandard("3.3-V LVTTL")) # Arduino_IO0
Subsignal("tx", Pins("AH9"), IOStandard("3.3-V LVTTL")), # user i/o port on mister i/o board
Subsignal("rx", Pins("AG11"), IOStandard("3.3-V LVTTL")) # user i/o port on mister i/o board
),
# ("serial", 0,
# Subsignal("tx", Pins("AF13"), IOStandard("3.3-V LVTTL")), # Arduino_IO1
# Subsignal("rx", Pins("AG13"), IOStandard("3.3-V LVTTL")) # Arduino_IO0
# ),
("g_sensor", 0,
Subsignal("int", Pins("A17")),
Subsignal("sclk", Pins("C18")),
@ -47,6 +55,7 @@ _io = [
IOStandard("3.3-V LVTTL")
),
# HDMI consists of HDMI + I2C for control + I2S for audio
("hdmi", 0,
Subsignal("tx_d_r", Pins("AS12 AE12 W8 Y8 AD11 AD10 AE11 Y5")),
Subsignal("tx_d_g", Pins("AF10 Y4 AE9 AB4 AE7 AF6 AF8 AF5")),
@ -56,36 +65,20 @@ _io = [
Subsignal("tx_hs", Pins("T8")),
Subsignal("tx_vs", Pins("V13")),
Subsignal("tx_int", Pins("AF11")),
Subsignal("i2s0", Pins("T13")),
Subsignal("mclk", Pins("U11")),
Subsignal("lrclk", Pins("T11")),
Subsignal("sclk", Pins("T12")),
IOStandard("3.3-V LVTTL")
),
("i2c", 0,
Subsignal("scl", Pins("U10")),
Subsignal("sda", Pins("AA4")),
IOStandard("3.3-V LVTTL")
),
("gpio_0", 0, Pins(
"V12 E8 W12 D11 D8 AH13 AF7 AH14",
"AF4 AH3 AD5 AG14 AE23 D12 AD20 C12",
"AD17 AC23 AC22 Y19 AB23 AA19 W11 AA18",
"W14 Y18 Y17 AB25 AB26 Y11 AA26 AA13",
"AA11"),
IOStandard("3.3-V LVTTL")
),
("gpio_1", 0, Pins(
"Y15 AC24 AA15 AD26 AG28 AF28 AE25 AF27",
"AG26 AH27 AG25 AH26 AH24 AF25 AG23 AF24",
"AG24 AH22 AH21 AG21 AH23 AA20 AF22 AE22",
"AG20 AF21 AH23 AA20 AF22 AE22 AG20 AF21",
"AG19 AH19 AG18 AH18 AF18 AF20 AG15 AE20",
"AE19 AE17"),
IOStandard("3.3-V LVTTL")
),
("arduino", 0, Pins(
"AG13 AF13 AG10 AG9 U14 U13 AG8 AH8",
"AF17 AE15 AF15 AG16 AH11 AH12 AH9 AG11",
"AH7"),
("i2s", 0,
Subsignal("i2s", Pins("T13")),
Subsignal("mclk", Pins("U11")),
Subsignal("lrclk", Pins("T11")),
Subsignal("sclk", Pins("T12")),
IOStandard("3.3-V LVTTL")
),
]
@ -115,6 +108,23 @@ _mister_sdram_module_io = [
Subsignal("miso", Pins("AF25")),
IOStandard("3.3-V LVTTL")
),
("mister_outputs", 0,
Subsignal("led_user", Pins("Y15")),
Subsignal("led_hdd", Pins("AA15")),
Subsignal("led_power", Pins("AG28")),
IOStandard("3.3-V LVTTL")
),
("vga", 0,
Subsignal("red", Pins("AE17 AE20 AF20 AH18 AH19 AF21")),
Subsignal("green", Pins("AE19 AG15 AF18 AG18 AG19 AG20")),
Subsignal("blue", Pins("AG21 AA20 AE22 AF22 AH23 AH21")),
Subsignal("hsync", Pins("AH22")),
Subsignal("vsync", Pins("AG24")),
Subsignal("en", Pins("AH27")),
IOStandard("3.3-V LVTTL")
),
]
# Platform -----------------------------------------------------------------------------------------

89
litex_boards/targets/de10nano.py
View File

@ -17,18 +17,60 @@ from litex.soc.cores.clock import CycloneVPLL
from litex.soc.integration.soc_core import *
from litex.soc.integration.soc_sdram import *
from litex.soc.integration.builder import *
# de10nano specific
from litex.soc.cores.led import LedChaser
from litedram.modules import AS4C16M16
# de10nano 128MB sdram
from litedram.modules import SDRAMModule
from litedram.modules import _TechnologyTimings
from litedram.modules import _SpeedgradeTimings
from litedram.phy import GENSDRPHY
# de10nano buses
from litex.soc.interconnect.axi import *
from litex.soc.interconnect import wishbone
# VGA terminal
from litevideo.terminal.core import Terminal
# MiSTer I/O definitions
# Light up the top user leds on the mister i/o board
class MiSTerOutputs(Module):
def __init__(self, pads):
if hasattr(pads, 'led_power'):
led_power_pin = Signal()
self.comb += pads.led_power.eq(0)
if hasattr(pads, 'led_user'):
led_user_pin = Signal()
self.comb += pads.led_user.eq(0)
if hasattr(pads, 'led_hdd'):
led_hdd_pin = Signal()
self.comb += pads.led_hdd.eq(0)
led_power_pin.eq(1)
led_user_pin.eq(0)
led_hdd_pin.eq(0)
# MiSTer 128MB SDRAM
class MiSTer128SDRAM(SDRAMModule): #4 x AS4C32M16 32MB=4*8192*512 (hopefully 128MB=4*32768*512 or 16*8192*512)
memtype = "SDR"
# geometry
nbanks = 4
nrows = 16384
ncols = 1024
# timings
technology_timings = _TechnologyTimings(tREFI=64e6/8192, tWTR=(2, None), tCCD=(1, None), tRRD=None)
speedgrade_timings = {"default": _SpeedgradeTimings(tRP=18, tRCD=18, tWR=12, tRFC=(None, 60), tFAW=None, tRAS=None)}
# CRG ----------------------------------------------------------------------------------------------
class _CRG(Module):
def __init__(self, platform, sys_clk_freq, with_sdram=False):
self.clock_domains.cd_sys = ClockDomain()
self.clock_domains.cd_sys_ps = ClockDomain(reset_less=True)
self.clock_domains.cd_vga = ClockDomain(reset_less=True)
# # #
# Clk / Rst
@ -39,7 +81,8 @@ class _CRG(Module):
pll.register_clkin(clk50, 50e6)
pll.create_clkout(self.cd_sys, sys_clk_freq)
pll.create_clkout(self.cd_sys_ps, sys_clk_freq, phase=90)
pll.create_clkout(self.cd_vga, 25e6)
# SDRAM clock
if with_sdram:
self.specials += DDROutput(1, 0, platform.request("sdram_clock"), ClockSignal("sys_ps"))
@ -58,7 +101,7 @@ class BaseSoC(SoCCore):
# Leds -------------------------------------------------------------------------------------
self.submodules.leds = LedChaser(
pads = Cat(*[platform.request("user_led", i) for i in range(6)]),
pads = Cat(*[platform.request("user_led", i) for i in range(8)]),
sys_clk_freq = sys_clk_freq)
self.add_csr("leds")
@ -72,14 +115,24 @@ class MiSTerSDRAMSoC(SoCCore):
SoCCore.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform, with_sdram=True)
self.submodules.crg = _CRG(platform, sys_clk_freq, with_sdram=True)
# Leds -------------------------------------------------------------------------------------
self.submodules.leds = LedChaser(
pads = Cat(*[platform.request("user_led", i) for i in range(8)]),
sys_clk_freq = sys_clk_freq)
self.add_csr("leds")
# mister user leds
self.submodules.mister_outputs = mister_outputs = MiSTerOutputs(platform.request("mister_outputs",0))
self.add_csr("mister_outputs")
# SDR SDRAM --------------------------------------------------------------------------------
if not self.integrated_main_ram_size:
self.submodules.sdrphy = GENSDRPHY(platform.request("sdram"))
self.add_sdram("sdram",
phy = self.sdrphy,
module = AS4C16M16(self.clk_freq, "1:1"),
module = MiSTer128SDRAM(self.clk_freq, "1:1"),
origin = self.mem_map["main_ram"],
size = kwargs.get("max_sdram_size", 0x40000000),
l2_cache_size = kwargs.get("l2_size", 8192),
@ -87,6 +140,28 @@ class MiSTerSDRAMSoC(SoCCore):
l2_cache_reverse = True
)
# VGA terminal
self.mem_map["terminal"] = 0x30000000
self.submodules.terminal = terminal = Terminal()
self.add_wb_slave(self.mem_map["terminal"], self.terminal.bus, 8896)
self.add_memory_region("terminal", self.mem_map["terminal"], 8896, type="cached+linker")
# Connect VGA pins
vga = platform.request("vga", 0)
self.comb += [
vga.vsync.eq(terminal.vsync),
vga.hsync.eq(terminal.hsync),
vga.red.eq(terminal.red[2:8]),
vga.green.eq(terminal.green[2:8]),
vga.blue.eq(terminal.blue[2:8])
]
vga.en.eq(1)
# self.add_csr("terminal")
# AXI Bus
# axibus = AXILiteInterface()
# Build --------------------------------------------------------------------------------------------
def main():
@ -95,7 +170,7 @@ def main():
parser.add_argument("--load", action="store_true", help="Load bitstream")
builder_args(parser)
soc_sdram_args(parser)
parser.add_argument("--with-mister-sdram", action="store_true", help="Enable MiSTer SDRAM expansion board")
parser.add_argument("--with-mister-sdram", action="store_true", help="Enable MiSTer SDRAM expansion board")
args = parser.parse_args()
if args.with_mister_sdram:
soc = MiSTerSDRAMSoC(**soc_sdram_argdict(args))