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targets/orangecrab: add fallback to bootloader when usr_btn is pressed for 1 second.

This commit is contained in:
Florent Kermarrec 2020-09-01 16:22:32 +02:00
parent b9ac72cf78
commit 9b6ed6bdf1
1 changed files with 12 additions and 0 deletions
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12
litex_boards/targets/orangecrab.py
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@ -11,6 +11,7 @@ import sys
import argparse
from migen import *
from migen.genlib.misc import WaitTimer
from migen.genlib.resetsync import AsyncResetSynchronizer
from litex_boards.platforms import orangecrab
@ -63,6 +64,11 @@ class _CRG(Module):
usb_pll.create_clkout(self.cd_usb_48, 48e6)
usb_pll.create_clkout(self.cd_usb_12, 12e6)
# FPGA Reset (press usr_btn for 1 second to fallback to bootlooader)
reset_timer = WaitTimer(sys_clk_freq)
self.submodules += reset_timer
self.comb += reset_timer.wait.eq(~rst_n)
self.comb += platform.request("rst_n").eq(reset_timer.done)
class _CRGSDRAM(Module):
def __init__(self, platform, sys_clk_freq, with_usb_pll=False):
@ -127,6 +133,12 @@ class _CRGSDRAM(Module):
usb_pll.create_clkout(self.cd_usb_48, 48e6)
usb_pll.create_clkout(self.cd_usb_12, 12e6)
# FPGA Reset (press usr_btn for 1 second to fallback to bootlooader)
reset_timer = WaitTimer(sys_clk_freq)
self.submodules += reset_timer
self.comb += reset_timer.wait.eq(~rst_n)
self.comb += platform.request("rst_n").eq(~reset_timer.done)
# BaseSoC ------------------------------------------------------------------------------------------
class BaseSoC(SoCCore):