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mnt_rkx7: Add I2C (For the SiI9022A).
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2 changed files with 12 additions and 0 deletions
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@ -56,6 +56,13 @@ _io = [
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Subsignal("tx_data", Pins("H18 H17 G19 F18"), IOStandard("LVCMOS33")),
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),
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# I2C
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("i2c", 0,
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Subsignal("scl", Pins("G12")),
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Subsignal("sda", Pins("A13")),
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IOStandard("LVCMOS18"),
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),
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# DDR3 SDRAM.
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("ddram", 0,
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Subsignal("a", Pins(
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@ -16,6 +16,7 @@ from litex_boards.platforms import mnt_rkx7
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from litex.soc.cores.clock import *
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from litex.soc.integration.soc_core import *
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from litex.soc.integration.builder import *
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from litex.soc.cores.bitbang import I2CMaster
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from litedram.modules import MT41K512M16 # FIXME: IS43TR16512B
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from litedram.phy import s7ddrphy
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@ -89,6 +90,10 @@ class BaseSoC(SoCCore):
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if with_etherbone:
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self.add_etherbone(phy=self.ethphy)
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# I2C --------------------------------------------------------------------------------------
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self.submodules.i2c = I2CMaster(platform.request("i2c"))
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# Build --------------------------------------------------------------------------------------------
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def main():
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