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nexys4ddr: fix eth/int_n pin (B8) and use 4-bit on vga.blue.

This commit is contained in:
Florent Kermarrec 2020-12-24 10:15:29 +01:00
parent 4162fb9945
commit 9beaf25822
2 changed files with 6 additions and 6 deletions
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8
litex_boards/platforms/nexys4ddr.py
View File

@ -126,17 +126,17 @@ _io = [
Subsignal("mdc", Pins("C9")),
Subsignal("mdio", Pins("A9")),
Subsignal("rx_er", Pins("C10")),
Subsignal("int_n", Pins("D8")),
Subsignal("int_n", Pins("B8")),
IOStandard("LVCMOS33")
),
# VGA
("vga", 0,
Subsignal("red", Pins("A4 C5 B4 A3")),
Subsignal("red", Pins("A4 C5 B4 A3")),
Subsignal("green", Pins("A6 B6 A5 C6")),
Subsignal("blue", Pins("D7 C7 B7")), # D8 is shared with eth int_n
Subsignal("blue", Pins("D7 C7 B7 D8")),
Subsignal("hsync", Pins("B11")),
Subsignal("vsync", Pins("B12")),
Subsignal("vsync", Pins("B12")),
IOStandard("LVCMOS33")
),
]

4
litex_boards/targets/nexys4ddr.py
View File

@ -48,7 +48,7 @@ class _CRG(Module):
pll.create_clkout(self.cd_sys2x_dqs, 2*sys_clk_freq, phase=90)
pll.create_clkout(self.cd_idelay, 200e6)
pll.create_clkout(self.cd_eth, 50e6)
pll.create_clkout(self.cd_vga, 25e6)
pll.create_clkout(self.cd_vga, 25e6)
self.submodules.idelayctrl = S7IDELAYCTRL(self.cd_idelay)
@ -102,7 +102,7 @@ class BaseSoC(SoCCore):
vga_pads.hsync.eq(terminal.hsync),
vga_pads.red.eq(terminal.red[4:8]),
vga_pads.green.eq(terminal.green[4:8]),
vga_pads.blue.eq(terminal.blue[3:8])
vga_pads.blue.eq(terminal.blue[4:8])
]
# Leds -------------------------------------------------------------------------------------