Hardware
/
litex-boards
mirror of https://github.com/litex-hub/litex-boards.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

nexys4ddr: fix eth/int_n pin (B8) and use 4-bit on vga.blue.

This commit is contained in:
Florent Kermarrec 2020-12-24 10:15:29 +01:00
parent 4162fb9945
commit 9beaf25822
2 changed files with 6 additions and 6 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
litex_boards/platforms/nexys4ddr.py
View File

@ -126,7 +126,7 @@ _io = [
Subsignal("mdc", Pins("C9")), Subsignal("mdc", Pins("C9")),
Subsignal("mdio", Pins("A9")), Subsignal("mdio", Pins("A9")),
Subsignal("rx_er", Pins("C10")), Subsignal("rx_er", Pins("C10")),
Subsignal("int_n", Pins("D8")), Subsignal("int_n", Pins("B8")),
IOStandard("LVCMOS33") IOStandard("LVCMOS33")
), ),
@ -134,7 +134,7 @@ _io = [
("vga", 0, ("vga", 0,
Subsignal("red", Pins("A4 C5 B4 A3")), Subsignal("red", Pins("A4 C5 B4 A3")),
Subsignal("green", Pins("A6 B6 A5 C6")), Subsignal("green", Pins("A6 B6 A5 C6")),
Subsignal("blue", Pins("D7 C7 B7")), # D8 is shared with eth int_n Subsignal("blue", Pins("D7 C7 B7 D8")),
Subsignal("hsync", Pins("B11")), Subsignal("hsync", Pins("B11")),
Subsignal("vsync", Pins("B12")), Subsignal("vsync", Pins("B12")),
IOStandard("LVCMOS33") IOStandard("LVCMOS33")

2
litex_boards/targets/nexys4ddr.py
View File

@ -102,7 +102,7 @@ class BaseSoC(SoCCore):
vga_pads.hsync.eq(terminal.hsync), vga_pads.hsync.eq(terminal.hsync),
vga_pads.red.eq(terminal.red[4:8]), vga_pads.red.eq(terminal.red[4:8]),
vga_pads.green.eq(terminal.green[4:8]), vga_pads.green.eq(terminal.green[4:8]),
vga_pads.blue.eq(terminal.blue[3:8]) vga_pads.blue.eq(terminal.blue[4:8])
] ]
# Leds ------------------------------------------------------------------------------------- # Leds -------------------------------------------------------------------------------------