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targets: Create target_group for target arguments.

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This commit is contained in:
Florent Kermarrec 2022-03-21 18:30:10 +01:00
parent d90e260414
commit 9d452b0d74
120 changed files with 825 additions and 709 deletions
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13
litex_boards/targets/1bitsquared_icebreaker.py
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@ -135,12 +135,13 @@ def flash(build_dir, build_name, bios_flash_offset):
def main():
from litex.soc.integration.soc import LiteXSoCArgumentParser
parser = LiteXSoCArgumentParser(description="LiteX SoC on iCEBreaker")
parser.add_argument("--build", action="store_true", help="Build bitstream.")
parser.add_argument("--load", action="store_true", help="Load bitstream.")
parser.add_argument("--flash", action="store_true", help="Flash Bitstream and BIOS.")
parser.add_argument("--sys-clk-freq", default=24e6, help="System clock frequency.")
parser.add_argument("--bios-flash-offset", default="0x40000", help="BIOS offset in SPI Flash.")
parser.add_argument("--with-video-terminal", action="store_true", help="Enable Video Terminal (with DVI PMOD).")
target_group = parser.add_argument_group(title="Target options")
target_group.add_argument("--build", action="store_true", help="Build bitstream.")
target_group.add_argument("--load", action="store_true", help="Load bitstream.")
target_group.add_argument("--flash", action="store_true", help="Flash Bitstream and BIOS.")
target_group.add_argument("--sys-clk-freq", default=24e6, help="System clock frequency.")
target_group.add_argument("--bios-flash-offset", default="0x40000", help="BIOS offset in SPI Flash.")
target_group.add_argument("--with-video-terminal", action="store_true", help="Enable Video Terminal (with DVI PMOD).")
builder_args(parser)
soc_core_args(parser)
args = parser.parse_args()

11
litex_boards/targets/1bitsquared_icebreaker_bitsy.py
View file

@ -110,11 +110,12 @@ class BaseSoC(SoCCore):
def main():
from litex.soc.integration.soc import LiteXSoCArgumentParser
parser = LiteXSoCArgumentParser(description="LiteX SoC on iCEBreaker")
parser.add_argument("--build", action="store_true", help="Build bitstream.")
parser.add_argument("--flash", action="store_true", help="Flash bitstream and BIOS.")
parser.add_argument("--sys-clk-freq", default=24e6, help="System clock frequency.")
parser.add_argument("--bios-flash-offset", default="0xa0000", help="BIOS offset in SPI Flash.")
parser.add_argument("--revision", default="v1", help="Board revision (v0 or v1).")
target_group = parser.add_argument_group(title="Target options")
target_group.add_argument("--build", action="store_true", help="Build bitstream.")
target_group.add_argument("--flash", action="store_true", help="Flash bitstream and BIOS.")
target_group.add_argument("--sys-clk-freq", default=24e6, help="System clock frequency.")
target_group.add_argument("--bios-flash-offset", default="0xa0000", help="BIOS offset in SPI Flash.")
target_group.add_argument("--revision", default="v1", help="Board revision (v0 or v1).")
builder_args(parser)
soc_core_args(parser)
args = parser.parse_args()

12
litex_boards/targets/adi_adrv2crr_fmc.py
View file

@ -125,12 +125,12 @@ class BaseSoC(SoCCore):
def main():
from litex.soc.integration.soc import LiteXSoCArgumentParser
parser = LiteXSoCArgumentParser(description="LiteX SoC on ADI ADRV2CRR-FMC")
parser.add_argument("--build", action="store_true", help="Build bitstream")
parser.add_argument("--load", action="store_true", help="Load bitstream.")
parser.add_argument("--sys-clk-freq", default=150e6, help="System clock frequency (default: 150 MHz)")
parser.add_argument("--with-pcie", action="store_true", help="Enable PCIe support")
parser.add_argument("--driver", action="store_true", help="Generate PCIe driver")
target_group = parser.add_argument_group(title="Target options")
target_group.add_argument("--build", action="store_true", help="Build bitstream")
target_group.add_argument("--load", action="store_true", help="Load bitstream.")
target_group.add_argument("--sys-clk-freq", default=150e6, help="System clock frequency (default: 150 MHz)")
target_group.add_argument("--with-pcie", action="store_true", help="Enable PCIe support")
target_group.add_argument("--driver", action="store_true", help="Generate PCIe driver")
builder_args(parser)
soc_core_args(parser)
args = parser.parse_args()

13
litex_boards/targets/alchitry_au.py
View file

@ -90,12 +90,13 @@ class BaseSoC(SoCCore):
def main():
from litex.soc.integration.soc import LiteXSoCArgumentParser
parser = LiteXSoCArgumentParser(description="LiteX SoC on Alchitry Au(+)")
parser.add_argument("--build", action="store_true", help="Build bitstream.")
parser.add_argument("--load", action="store_true", help="Load bitstream.")
parser.add_argument("--flash", action="store_true", help="Flash bitstream.")
parser.add_argument("--variant", default="au", help="Board variant (au or au+).")
parser.add_argument("--sys-clk-freq", default=83333333, help="System clock frequency.")
parser.add_argument("--with-spi-flash", action="store_true", help="Enable SPI Flash (MMAPed).")
target_group = parser.add_argument_group(title="Target options")
target_group.add_argument("--build", action="store_true", help="Build bitstream.")
target_group.add_argument("--load", action="store_true", help="Load bitstream.")
target_group.add_argument("--flash", action="store_true", help="Flash bitstream.")
target_group.add_argument("--variant", default="au", help="Board variant (au or au+).")
target_group.add_argument("--sys-clk-freq", default=83333333, help="System clock frequency.")
target_group.add_argument("--with-spi-flash", action="store_true", help="Enable SPI Flash (MMAPed).")
builder_args(parser)
soc_core_args(parser)
vivado_build_args(parser)

12
litex_boards/targets/alchitry_mojo.py
View file

@ -145,17 +145,17 @@ class BaseSoC(SoCCore):
def main():
from litex.soc.integration.soc import LiteXSoCArgumentParser
parser = LiteXSoCArgumentParser(description="LiteX SoC on Alchitry Mojo")
parser.add_argument("--build", action="store_true", help="Build bitstream.")
parser.add_argument("--sys-clk-freq", default=62.5e6, help="System clock frequency.")
parser.add_argument("--sdram-rate", default="1:1", help="SDRAM Rate: (1:1 Full Rate or 1:2 Half Rate).")
shields1 = parser.add_mutually_exclusive_group()
target_group = parser.add_argument_group(title="Target options")
target_group.add_argument("--build", action="store_true", help="Build bitstream.")
target_group.add_argument("--sys-clk-freq", default=62.5e6, help="System clock frequency.")
target_group.add_argument("--sdram-rate", default="1:1", help="SDRAM Rate: (1:1 Full Rate or 1:2 Half Rate).")
shields1 = target_group.add_mutually_exclusive_group()
shields1.add_argument("--with-hdmi-shield", action="store_true", help="Enable HDMI Shield.")
shields1.add_argument("--with-sdram-shield", action="store_true", help="Enable SDRAM Shield.")
viopts = parser.add_mutually_exclusive_group()
viopts = target_group.add_mutually_exclusive_group()
viopts.add_argument("--with-video-terminal", action="store_true", help="Enable Video Terminal (HDMI).")
viopts.add_argument("--with-video-framebuffer", action="store_true", help="Enable Video Framebuffer (HDMI).")
viopts.add_argument("--with-video-colorbars", action="store_true", help="Enable Video Colorbars (HDMI).")
builder_args(parser)
soc_core_args(parser)
args = parser.parse_args()

7
litex_boards/targets/alinx_ax7010.py
View file

@ -60,9 +60,10 @@ class BaseSoC(SoCCore):
def main():
from litex.soc.integration.soc import LiteXSoCArgumentParser
parser = LiteXSoCArgumentParser(description="LiteX SoC on zynq xc7z010")
parser.add_argument("--build", action="store_true", help="Build bitstream")
parser.add_argument("--load", action="store_true", help="Load bitstream")
parser.add_argument("--sys-clk-freq", default=100e6, help="System clock frequency (default: 100MHz)")
target_group = parser.add_argument_group(title="Target options")
target_group.add_argument("--build", action="store_true", help="Build bitstream")
target_group.add_argument("--load", action="store_true", help="Load bitstream")
target_group.add_argument("--sys-clk-freq", default=100e6, help="System clock frequency (default: 100MHz)")
builder_args(parser)
soc_core_args(parser)
vivado_build_args(parser)

9
litex_boards/targets/alinx_axu2cga.py
View file

@ -179,10 +179,11 @@ class BaseSoC(SoCCore):
def main():
from litex.soc.integration.soc import LiteXSoCArgumentParser
parser = LiteXSoCArgumentParser(description="LiteX SoC on Alinx AXU2CGA")
parser.add_argument("--build", action="store_true", help="Build bitstream.")
parser.add_argument("--load", action="store_true", help="Load bitstream.")
parser.add_argument("--cable", default="ft232", help="JTAG interface.")
parser.add_argument("--sys-clk-freq", default=25e6, help="System clock frequency.")
target_group = parser.add_argument_group(title="Target options")
target_group.add_argument("--build", action="store_true", help="Build bitstream.")
target_group.add_argument("--load", action="store_true", help="Load bitstream.")
target_group.add_argument("--cable", default="ft232", help="JTAG interface.")
target_group.add_argument("--sys-clk-freq", default=25e6, help="System clock frequency.")
builder_args(parser)
soc_core_args(parser)
vivado_build_args(parser)

28
litex_boards/targets/antmicro_datacenter_ddr4_test_board.py
View file

@ -150,22 +150,22 @@ class LiteDRAMSettingsEncoder(json.JSONEncoder):
def main():
from litex.soc.integration.soc import LiteXSoCArgumentParser
parser = LiteXSoCArgumentParser(description="LiteX SoC on LPDDR4 Test Board")
target = parser.add_argument_group(title="Target options")
target.add_argument("--build", action="store_true", help="Build bitstream.")
target.add_argument("--load", action="store_true", help="Load bitstream.")
target.add_argument("--flash", action="store_true", help="Flash bitstream.")
target.add_argument("--sys-clk-freq", default=100e6, help="System clock frequency.")
target.add_argument("--iodelay-clk-freq", default=200e6, help="IODELAYCTRL frequency.")
ethopts = target.add_mutually_exclusive_group()
target_group = parser.add_argument_group(title="Target options")
target_group.add_argument("--build", action="store_true", help="Build bitstream.")
target_group.add_argument("--load", action="store_true", help="Load bitstream.")
target_group.add_argument("--flash", action="store_true", help="Flash bitstream.")
target_group.add_argument("--sys-clk-freq", default=100e6, help="System clock frequency.")
target_group.add_argument("--iodelay-clk-freq", default=200e6, help="IODELAYCTRL frequency.")
ethopts = target_group.add_mutually_exclusive_group()
ethopts.add_argument("--with-ethernet", action="store_true", help="Add Ethernet.")
ethopts.add_argument("--with-etherbone", action="store_true", help="Add EtherBone.")
target.add_argument("--eth-ip", default="192.168.1.50", help="Ethernet/Etherbone IP address.")
target.add_argument("--eth-dynamic-ip", action="store_true", help="Enable dynamic Ethernet IP addresses setting.")
target.add_argument("--eth-reset-time", default="10e-3", help="Duration of Ethernet PHY reset")
target.add_argument("--with-hyperram", action="store_true", help="Add HyperRAM.")
target.add_argument("--with-sdcard", action="store_true", help="Add SDCard.")
target.add_argument("--with-jtagbone", action="store_true", help="Add JTAGBone.")
target.add_argument("--with-uartbone", action="store_true", help="Add UartBone on 2nd serial.")
target_group.add_argument("--eth-ip", default="192.168.1.50", help="Ethernet/Etherbone IP address.")
target_group.add_argument("--eth-dynamic-ip", action="store_true", help="Enable dynamic Ethernet IP addresses setting.")
target_group.add_argument("--eth-reset-time", default="10e-3", help="Duration of Ethernet PHY reset")
target_group.add_argument("--with-hyperram", action="store_true", help="Add HyperRAM.")
target_group.add_argument("--with-sdcard", action="store_true", help="Add SDCard.")
target_group.add_argument("--with-jtagbone", action="store_true", help="Add JTAGBone.")
target_group.add_argument("--with-uartbone", action="store_true", help="Add UartBone on 2nd serial.")
builder_args(parser)
soc_core_args(parser)
vivado_build_args(parser)

26
litex_boards/targets/antmicro_lpddr4_test_board.py
View file

@ -115,21 +115,21 @@ class BaseSoC(SoCCore):
def main():
from litex.soc.integration.soc import LiteXSoCArgumentParser
parser = LiteXSoCArgumentParser(description="LiteX SoC on LPDDR4 Test Board")
target = parser.add_argument_group(title="Target options")
target.add_argument("--build", action="store_true", help="Build bitstream.")
target.add_argument("--load", action="store_true", help="Load bitstream.")
target.add_argument("--flash", action="store_true", help="Flash bitstream.")
target.add_argument("--sys-clk-freq", default=50e6, help="System clock frequency.")
target.add_argument("--iodelay-clk-freq", default=200e6, help="IODELAYCTRL frequency.")
ethopts = target.add_mutually_exclusive_group()
target_group = parser.add_argument_group(title="Target options")
target_group.add_argument("--build", action="store_true", help="Build bitstream.")
target_group.add_argument("--load", action="store_true", help="Load bitstream.")
target_group.add_argument("--flash", action="store_true", help="Flash bitstream.")
target_group.add_argument("--sys-clk-freq", default=50e6, help="System clock frequency.")
target_group.add_argument("--iodelay-clk-freq", default=200e6, help="IODELAYCTRL frequency.")
ethopts = target_group.add_mutually_exclusive_group()
ethopts.add_argument("--with-ethernet", action="store_true", help="Add Ethernet.")
ethopts.add_argument("--with-etherbone", action="store_true", help="Add EtherBone.")
target.add_argument("--eth-ip", default="192.168.1.50", help="Ethernet/Etherbone IP address.")
target.add_argument("--eth-dynamic-ip", action="store_true", help="Enable dynamic Ethernet IP addresses setting.")
target.add_argument("--with-hyperram", action="store_true", help="Add HyperRAM.")
target.add_argument("--with-sdcard", action="store_true", help="Add SDCard.")
target.add_argument("--with-jtagbone", action="store_true", help="Add JTAGBone.")
target.add_argument("--with-uartbone", action="store_true", help="Add UartBone on 2nd serial.")
target_group.add_argument("--eth-ip", default="192.168.1.50", help="Ethernet/Etherbone IP address.")
target_group.add_argument("--eth-dynamic-ip", action="store_true", help="Enable dynamic Ethernet IP addresses setting.")
target_group.add_argument("--with-hyperram", action="store_true", help="Add HyperRAM.")
target_group.add_argument("--with-sdcard", action="store_true", help="Add SDCard.")
target_group.add_argument("--with-jtagbone", action="store_true", help="Add JTAGBone.")
target_group.add_argument("--with-uartbone", action="store_true", help="Add UartBone on 2nd serial.")
builder_args(parser)
soc_core_args(parser)
vivado_build_args(parser)

17
litex_boards/targets/berkeleylab_marble.py
View file

@ -148,14 +148,15 @@ class BaseSoC(SoCCore):
def main():
from litex.soc.integration.soc import LiteXSoCArgumentParser
parser = LiteXSoCArgumentParser(description="LiteX SoC on BerkeleyLab Marble")
parser.add_argument("--build", action="store_true", help="Build bitstream.")
parser.add_argument("--load", action="store_true", help="Load bitstream.")
parser.add_argument("--sys-clk-freq", default=125e6, help="System clock frequency.")
parser.add_argument("--with-ethernet", action="store_true", help="Enable Ethernet support.")
parser.add_argument("--with-etherbone", action="store_true", help="Enable Etherbone support.")
parser.add_argument("--with-rts-reset", action="store_true", help="Connect UART RTS line to sys_clk reset.")
parser.add_argument("--with-bist", action="store_true", help="Add DDR3 BIST Generator/Checker.")
parser.add_argument("--spd-dump", type=str, help="DDR3 configuration file, dumped using the `spdread` command in LiteX BIOS.")
target_group = parser.add_argument_group(title="Target options")
target_group.add_argument("--build", action="store_true", help="Build bitstream.")
target_group.add_argument("--load", action="store_true", help="Load bitstream.")
target_group.add_argument("--sys-clk-freq", default=125e6, help="System clock frequency.")
target_group.add_argument("--with-ethernet", action="store_true", help="Enable Ethernet support.")
target_group.add_argument("--with-etherbone", action="store_true", help="Enable Etherbone support.")
target_group.add_argument("--with-rts-reset", action="store_true", help="Connect UART RTS line to sys_clk reset.")
target_group.add_argument("--with-bist", action="store_true", help="Add DDR3 BIST Generator/Checker.")
target_group.add_argument("--spd-dump", type=str, help="DDR3 configuration file, dumped using the `spdread` command in LiteX BIOS.")
builder_args(parser)
soc_core_args(parser)
args = parser.parse_args()

9
litex_boards/targets/camlink_4k.py
View file

@ -105,10 +105,11 @@ class BaseSoC(SoCCore):
def main():
from litex.soc.integration.soc import LiteXSoCArgumentParser
parser = LiteXSoCArgumentParser(description="LiteX SoC on Cam Link 4K")
parser.add_argument("--build", action="store_true", help="Build bitstream.")
parser.add_argument("--load", action="store_true", help="Load bitstream.")
parser.add_argument("--sys-clk-freq", default=81e6, help="System clock frequency.")
parser.add_argument("--toolchain", default="trellis", help="FPGA toolchain (trellis or diamond).")
target_group = parser.add_argument_group(title="Target options")
target_group.add_argument("--build", action="store_true", help="Build bitstream.")
target_group.add_argument("--load", action="store_true", help="Load bitstream.")
target_group.add_argument("--sys-clk-freq", default=81e6, help="System clock frequency.")
target_group.add_argument("--toolchain", default="trellis", help="FPGA toolchain (trellis or diamond).")
builder_args(parser)
soc_core_args(parser)
trellis_args(parser)

21
litex_boards/targets/colorlight_5a_75x.py
View file

@ -177,18 +177,19 @@ class BaseSoC(SoCCore):
def main():
from litex.soc.integration.soc import LiteXSoCArgumentParser
parser = LiteXSoCArgumentParser(description="LiteX SoC on Colorlight 5A-75X")
parser.add_argument("--build", action="store_true", help="Build bitstream.")
parser.add_argument("--load", action="store_true", help="Load bitstream.")
parser.add_argument("--board", default="5a-75b", help="Board type (5a-75b or 5a-75e).")
parser.add_argument("--revision", default="7.0", type=str, help="Board revision (6.0, 6.1, 7.0 or 8.0).")
parser.add_argument("--sys-clk-freq", default=60e6, help="System clock frequency")
ethopts = parser.add_mutually_exclusive_group()
target_group = parser.add_argument_group(title="Target options")
target_group.add_argument("--build", action="store_true", help="Build bitstream.")
target_group.add_argument("--load", action="store_true", help="Load bitstream.")
target_group.add_argument("--board", default="5a-75b", help="Board type (5a-75b or 5a-75e).")
target_group.add_argument("--revision", default="7.0", type=str, help="Board revision (6.0, 6.1, 7.0 or 8.0).")
target_group.add_argument("--sys-clk-freq", default=60e6, help="System clock frequency")
ethopts = target_group.add_mutually_exclusive_group()
ethopts.add_argument("--with-ethernet", action="store_true", help="Enable Ethernet support.")
ethopts.add_argument("--with-etherbone", action="store_true", help="Enable Etherbone support.")
parser.add_argument("--eth-ip", default="192.168.1.50", type=str, help="Ethernet/Etherbone IP address.")
parser.add_argument("--eth-phy", default=0, type=int, help="Ethernet PHY (0 or 1).")
parser.add_argument("--use-internal-osc", action="store_true", help="Use internal oscillator.")
parser.add_argument("--sdram-rate", default="1:1", help="SDRAM Rate (1:1 Full Rate or 1:2 Half Rate).")
target_group.add_argument("--eth-ip", default="192.168.1.50", type=str, help="Ethernet/Etherbone IP address.")
target_group.add_argument("--eth-phy", default=0, type=int, help="Ethernet PHY (0 or 1).")
target_group.add_argument("--use-internal-osc", action="store_true", help="Use internal oscillator.")
target_group.add_argument("--sdram-rate", default="1:1", help="SDRAM Rate (1:1 Full Rate or 1:2 Half Rate).")
builder_args(parser)
soc_core_args(parser)
trellis_args(parser)

27
litex_boards/targets/colorlight_i5.py
View file

@ -174,23 +174,24 @@ class BaseSoC(SoCCore):
def main():
from litex.soc.integration.soc import LiteXSoCArgumentParser
parser = LiteXSoCArgumentParser(description="LiteX SoC on Colorlight I5")
parser.add_argument("--build", action="store_true", help="Build bitstream.")
parser.add_argument("--load", action="store_true", help="Load bitstream.")
parser.add_argument("--board", default="i5", help="Board type (i5).")
parser.add_argument("--revision", default="7.0", type=str, help="Board revision (7.0).")
parser.add_argument("--sys-clk-freq", default=60e6, help="System clock frequency.")
ethopts = parser.add_mutually_exclusive_group()
target_group = parser.add_argument_group(title="Target options")
target_group.add_argument("--build", action="store_true", help="Build bitstream.")
target_group.add_argument("--load", action="store_true", help="Load bitstream.")
target_group.add_argument("--board", default="i5", help="Board type (i5).")
target_group.add_argument("--revision", default="7.0", type=str, help="Board revision (7.0).")
target_group.add_argument("--sys-clk-freq", default=60e6, help="System clock frequency.")
ethopts = target_group.add_mutually_exclusive_group()
ethopts.add_argument("--with-ethernet", action="store_true", help="Enable Ethernet support.")
ethopts.add_argument("--with-etherbone", action="store_true", help="Enable Etherbone support.")
parser.add_argument("--remote-ip", default="192.168.1.100", help="Remote IP address of TFTP server.")
parser.add_argument("--local-ip", default="192.168.1.50", help="Local IP address.")
sdopts = parser.add_mutually_exclusive_group()
target_group.add_argument("--remote-ip", default="192.168.1.100", help="Remote IP address of TFTP server.")
target_group.add_argument("--local-ip", default="192.168.1.50", help="Local IP address.")
sdopts = target_group.add_mutually_exclusive_group()
sdopts.add_argument("--with-spi-sdcard", action="store_true", help="Enable SPI-mode SDCard support.")
sdopts.add_argument("--with-sdcard", action="store_true", help="Enable SDCard support.")
parser.add_argument("--eth-phy", default=0, type=int, help="Ethernet PHY (0 or 1).")
parser.add_argument("--use-internal-osc", action="store_true", help="Use internal oscillator.")
parser.add_argument("--sdram-rate", default="1:1", help="SDRAM Rate (1:1 Full Rate or 1:2 Half Rate).")
viopts = parser.add_mutually_exclusive_group()
target_group.add_argument("--eth-phy", default=0, type=int, help="Ethernet PHY (0 or 1).")
target_group.add_argument("--use-internal-osc", action="store_true", help="Use internal oscillator.")
target_group.add_argument("--sdram-rate", default="1:1", help="SDRAM Rate (1:1 Full Rate or 1:2 Half Rate).")
viopts = target_group.add_mutually_exclusive_group()
viopts.add_argument("--with-video-terminal", action="store_true", help="Enable Video Terminal (HDMI).")
viopts.add_argument("--with-video-framebuffer", action="store_true", help="Enable Video Framebuffer (HDMI).")
builder_args(parser)

11
litex_boards/targets/decklink_intensity_pro_4k.py
View file

@ -64,11 +64,12 @@ class BaseSoC(SoCCore):
def main():
from litex.soc.integration.soc import LiteXSoCArgumentParser
parser = LiteXSoCArgumentParser(description="LiteX SoC Blackmagic Decklink Intensity Pro 4K")
parser.add_argument("--build", action="store_true", help="Build bitstream.")
parser.add_argument("--load", action="store_true", help="Load bitstream.")
parser.add_argument("--sys-clk-freq", default=125e6, help="System clock frequency.")
parser.add_argument("--with-pcie", action="store_true", help="Enable PCIe support.")
parser.add_argument("--driver", action="store_true", help="Generate PCIe driver.")
target_group = parser.add_argument_group(title="Target options")
target_group.add_argument("--build", action="store_true", help="Build bitstream.")
target_group.add_argument("--load", action="store_true", help="Load bitstream.")
target_group.add_argument("--sys-clk-freq", default=125e6, help="System clock frequency.")
target_group.add_argument("--with-pcie", action="store_true", help="Enable PCIe support.")
target_group.add_argument("--driver", action="store_true", help="Generate PCIe driver.")
builder_args(parser)
soc_core_args(parser)
vivado_build_args(parser)

13
litex_boards/targets/decklink_mini_4k.py
View file

@ -151,13 +151,14 @@ class BaseSoC(SoCMini):
def main():
from litex.soc.integration.soc import LiteXSoCArgumentParser
parser = LiteXSoCArgumentParser(description="LiteX SoC Blackmagic Decklink Mini 4K")
parser.add_argument("--build", action="store_true", help="Build bitstream.")
parser.add_argument("--load", action="store_true", help="Load bitstream.")
parser.add_argument("--sys-clk-freq", default=148.5e6, help="System clock frequency.")
pcieopts = parser.add_mutually_exclusive_group()
target_group = parser.add_argument_group(title="Target options")
target_group.add_argument("--build", action="store_true", help="Build bitstream.")
target_group.add_argument("--load", action="store_true", help="Load bitstream.")
target_group.add_argument("--sys-clk-freq", default=148.5e6, help="System clock frequency.")
pcieopts = target_group.add_mutually_exclusive_group()
pcieopts.add_argument("--with-pcie", action="store_true", help="Enable PCIe support.")
parser.add_argument("--driver", action="store_true", help="Generate PCIe driver.")
viopts = parser.add_mutually_exclusive_group()
target_group.add_argument("--driver", action="store_true", help="Generate PCIe driver.")
viopts = target_group.add_mutually_exclusive_group()
viopts.add_argument("--with-video-terminal", action="store_true", help="Enable Video Terminal (HDMI).")
viopts.add_argument("--with-video-framebuffer", action="store_true", help="Enable Video Framebuffer (HDMI).")
pcieopts.add_argument("--with-sata", action="store_true", help="Enable SATA support (over PCIe2SATA).")

11
litex_boards/targets/decklink_quad_hdmi_recorder.py
View file

@ -102,11 +102,12 @@ class BaseSoC(SoCCore):
def main():
from litex.soc.integration.soc import LiteXSoCArgumentParser
parser = LiteXSoCArgumentParser(description="LiteX SoC on Blackmagic Decklink Quad HDMI Recorder")
parser.add_argument("--build", action="store_true", help="Build bitstream.")
parser.add_argument("--load", action="store_true", help="Load bitstream.")
parser.add_argument("--sys-clk-freq", default=200e6, help="System clock frequency.")
parser.add_argument("--with-pcie", action="store_true", help="Enable PCIe support.")
parser.add_argument("--driver", action="store_true", help="Generate PCIe driver.")
target_group = parser.add_argument_group(title="Target options")
target_group.add_argument("--build", action="store_true", help="Build bitstream.")
target_group.add_argument("--load", action="store_true", help="Load bitstream.")
target_group.add_argument("--sys-clk-freq", default=200e6, help="System clock frequency.")
target_group.add_argument("--with-pcie", action="store_true", help="Enable PCIe support.")
target_group.add_argument("--driver", action="store_true", help="Generate PCIe driver.")
builder_args(parser)
soc_core_args(parser)
args = parser.parse_args()

29
litex_boards/targets/digilent_arty.py
View file

@ -129,24 +129,25 @@ class BaseSoC(SoCCore):
def main():
from litex.soc.integration.soc import LiteXSoCArgumentParser
parser = LiteXSoCArgumentParser(description="LiteX SoC on Arty A7")
parser.add_argument("--toolchain", default="vivado", help="FPGA toolchain (vivado, symbiflow or yosys+nextpnr).")
parser.add_argument("--build", action="store_true", help="Build bitstream.")
parser.add_argument("--load", action="store_true", help="Load bitstream.")
parser.add_argument("--flash", action="store_true", help="Flash bitstream.")
parser.add_argument("--variant", default="a7-35", help="Board variant (a7-35 or a7-100).")
parser.add_argument("--sys-clk-freq", default=100e6, help="System clock frequency.")
ethopts = parser.add_mutually_exclusive_group()
target_group = parser.add_argument_group(title="Target options")
target_group.add_argument("--toolchain", default="vivado", help="FPGA toolchain (vivado, symbiflow or yosys+nextpnr).")
target_group.add_argument("--build", action="store_true", help="Build bitstream.")
target_group.add_argument("--load", action="store_true", help="Load bitstream.")
target_group.add_argument("--flash", action="store_true", help="Flash bitstream.")
target_group.add_argument("--variant", default="a7-35", help="Board variant (a7-35 or a7-100).")
target_group.add_argument("--sys-clk-freq", default=100e6, help="System clock frequency.")
ethopts = target_group.add_mutually_exclusive_group()
ethopts.add_argument("--with-ethernet", action="store_true", help="Enable Ethernet support.")
ethopts.add_argument("--with-etherbone", action="store_true", help="Enable Etherbone support.")
parser.add_argument("--eth-ip", default="192.168.1.50", type=str, help="Ethernet/Etherbone IP address.")
parser.add_argument("--eth-dynamic-ip", action="store_true", help="Enable dynamic Ethernet IP addresses setting.")
sdopts = parser.add_mutually_exclusive_group()
target_group.add_argument("--eth-ip", default="192.168.1.50", type=str, help="Ethernet/Etherbone IP address.")
target_group.add_argument("--eth-dynamic-ip", action="store_true", help="Enable dynamic Ethernet IP addresses setting.")
sdopts = target_group.add_mutually_exclusive_group()
sdopts.add_argument("--with-spi-sdcard", action="store_true", help="Enable SPI-mode SDCard support.")
sdopts.add_argument("--with-sdcard", action="store_true", help="Enable SDCard support.")
parser.add_argument("--sdcard-adapter", type=str, help="SDCard PMOD adapter (digilent or numato).")
parser.add_argument("--with-jtagbone", action="store_true", help="Enable JTAGbone support.")
parser.add_argument("--with-spi-flash", action="store_true", help="Enable SPI Flash (MMAPed).")
parser.add_argument("--with-pmod-gpio", action="store_true", help="Enable GPIOs through PMOD.") # FIXME: Temporary test.
target_group.add_argument("--sdcard-adapter", type=str, help="SDCard PMOD adapter (digilent or numato).")
target_group.add_argument("--with-jtagbone", action="store_true", help="Enable JTAGbone support.")
target_group.add_argument("--with-spi-flash", action="store_true", help="Enable SPI Flash (MMAPed).")
target_group.add_argument("--with-pmod-gpio", action="store_true", help="Enable GPIOs through PMOD.") # FIXME: Temporary test.
builder_args(parser)
soc_core_args(parser)
vivado_build_args(parser)

11
litex_boards/targets/digilent_arty_s7.py
View file

@ -88,11 +88,12 @@ class BaseSoC(SoCCore):
def main():
from litex.soc.integration.soc import LiteXSoCArgumentParser
parser = LiteXSoCArgumentParser(description="LiteX SoC on Arty S7")
parser.add_argument("--build", action="store_true", help="Build bitstream.")
parser.add_argument("--load", action="store_true", help="Load bitstream.")
parser.add_argument("--variant", default="s7-50", help="Board variant (s7-50 or s7-25).")
parser.add_argument("--sys-clk-freq", default=100e6, help="System clock frequency.")
parser.add_argument("--with-spi-flash", action="store_true", help="Enable SPI Flash (MMAPed).")
target_group = parser.add_argument_group(title="Target options")
target_group.add_argument("--build", action="store_true", help="Build bitstream.")
target_group.add_argument("--load", action="store_true", help="Load bitstream.")
target_group.add_argument("--variant", default="s7-50", help="Board variant (s7-50 or s7-25).")
target_group.add_argument("--sys-clk-freq", default=100e6, help="System clock frequency.")
target_group.add_argument("--with-spi-flash", action="store_true", help="Enable SPI Flash (MMAPed).")
builder_args(parser)
soc_core_args(parser)
vivado_build_args(parser)

11
litex_boards/targets/digilent_arty_z7.py
View file

@ -102,11 +102,12 @@ class BaseSoC(SoCCore):
def main():
from litex.soc.integration.soc import LiteXSoCArgumentParser
parser = LiteXSoCArgumentParser(description="LiteX SoC on Arty Z7")
parser.add_argument("--toolchain", default="vivado", help="FPGA toolchain (vivado, symbiflow or yosys+nextpnr).")
parser.add_argument("--build", action="store_true", help="Build bitstream.")
parser.add_argument("--load", action="store_true", help="Load bitstream.")
parser.add_argument("--variant", default="z7-20", help="Board variant (z7-20 or z7-10).")
parser.add_argument("--sys-clk-freq", default=125e6, help="System clock frequency.")
target_group = parser.add_argument_group(title="Target options")
target_group.add_argument("--toolchain", default="vivado", help="FPGA toolchain (vivado, symbiflow or yosys+nextpnr).")
target_group.add_argument("--build", action="store_true", help="Build bitstream.")
target_group.add_argument("--load", action="store_true", help="Load bitstream.")
target_group.add_argument("--variant", default="z7-20", help="Board variant (z7-20 or z7-10).")
target_group.add_argument("--sys-clk-freq", default=125e6, help="System clock frequency.")
builder_args(parser)
soc_core_args(parser)
vivado_build_args(parser)

9
litex_boards/targets/digilent_atlys.py
View file

@ -208,10 +208,11 @@ NET "{eth_clocks_tx}" CLOCK_DEDICATED_ROUTE = FALSE;
def main():
from litex.soc.integration.soc import LiteXSoCArgumentParser
parser = LiteXSoCArgumentParser(description="LiteX SoC on Atlys")
parser.add_argument("--build", action="store_true", help="Build bitstream.")
parser.add_argument("--load", action="store_true", help="Load bitstream.")
parser.add_argument("--with-ethernet", action="store_true", help="Enable Ethernet support.")
parser.add_argument("--with-etherbone", action="store_true", help="Enable Etherbone support.")
target_group = parser.add_argument_group(title="Target options")
target_group.add_argument("--build", action="store_true", help="Build bitstream.")
target_group.add_argument("--load", action="store_true", help="Load bitstream.")
target_group.add_argument("--with-ethernet", action="store_true", help="Enable Ethernet support.")
target_group.add_argument("--with-etherbone", action="store_true", help="Enable Etherbone support.")
builder_args(parser)
soc_core_args(parser)

13
litex_boards/targets/digilent_basys3.py
View file

@ -64,14 +64,15 @@ class BaseSoC(SoCCore):
def main():
from litex.soc.integration.soc import LiteXSoCArgumentParser
parser = LiteXSoCArgumentParser(description="LiteX SoC on Basys3")
parser.add_argument("--build", action="store_true", help="Build bitstream.")
parser.add_argument("--load", action="store_true", help="Load bitstream.")
parser.add_argument("--sys-clk-freq", default=75e6, help="System clock frequency.")
sdopts = parser.add_mutually_exclusive_group()
target_group = parser.add_argument_group(title="Target options")
target_group.add_argument("--build", action="store_true", help="Build bitstream.")
target_group.add_argument("--load", action="store_true", help="Load bitstream.")
target_group.add_argument("--sys-clk-freq", default=75e6, help="System clock frequency.")
sdopts = target_group.add_mutually_exclusive_group()
sdopts.add_argument("--with-spi-sdcard", action="store_true", help="Enable SPI-mode SDCard support.")
sdopts.add_argument("--with-sdcard", action="store_true", help="Enable SDCard support.")
parser.add_argument("--sdcard-adapter", type=str, help="SDCard PMOD adapter (digilent or numato).")
viopts = parser.add_mutually_exclusive_group()
target_group.add_argument("--sdcard-adapter", type=str, help="SDCard PMOD adapter (digilent or numato).")
viopts = target_group.add_mutually_exclusive_group()
viopts.add_argument("--with-video-terminal", action="store_true", help="Enable Video Terminal (VGA).")
builder_args(parser)
soc_core_args(parser)

15
litex_boards/targets/digilent_cmod_a7.py
View file

@ -137,13 +137,14 @@ class BaseSoC(SoCCore):
def main():
from litex.soc.integration.soc import LiteXSoCArgumentParser
parser = LiteXSoCArgumentParser(description="LiteX SoC on CMOD A7")
parser.add_argument("--toolchain", default="vivado", help="FPGA toolchain (vivado or symbiflow).")
parser.add_argument("--build", action="store_true", help="Build bitstream.")
parser.add_argument("--load", action="store_true", help="Load bitstream.")
parser.add_argument("--flash", action="store_true", help="Flash bitstream.")
parser.add_argument("--variant", default="a7-35", help="Board variant (a7-35 or a7-100).")
parser.add_argument("--sys-clk-freq", default=48e6, help="System clock frequency.")
parser.add_argument("--with-spi-flash", action="store_true", help="Enable SPI Flash (MMAPed).")
target_group = parser.add_argument_group(title="Target options")
target_group.add_argument("--toolchain", default="vivado", help="FPGA toolchain (vivado or symbiflow).")
target_group.add_argument("--build", action="store_true", help="Build bitstream.")
target_group.add_argument("--load", action="store_true", help="Load bitstream.")
target_group.add_argument("--flash", action="store_true", help="Flash bitstream.")
target_group.add_argument("--variant", default="a7-35", help="Board variant (a7-35 or a7-100).")
target_group.add_argument("--sys-clk-freq", default=48e6, help="System clock frequency.")
target_group.add_argument("--with-spi-flash", action="store_true", help="Enable SPI Flash (MMAPed).")
builder_args(parser)

11
litex_boards/targets/digilent_genesys2.py
View file

@ -89,13 +89,14 @@ class BaseSoC(SoCCore):
def main():
from litex.soc.integration.soc import LiteXSoCArgumentParser
parser = LiteXSoCArgumentParser(description="LiteX SoC on Genesys2")
parser.add_argument("--build", action="store_true", help="Build bitstream.")
parser.add_argument("--load", action="store_true", help="Load bitstream.")
parser.add_argument("--sys-clk-freq", default=100e6, help="System clock frequency.")
ethopts = parser.add_mutually_exclusive_group()
target_group = parser.add_argument_group(title="Target options")
target_group.add_argument("--build", action="store_true", help="Build bitstream.")
target_group.add_argument("--load", action="store_true", help="Load bitstream.")
target_group.add_argument("--sys-clk-freq", default=100e6, help="System clock frequency.")
ethopts = target_group.add_mutually_exclusive_group()
ethopts.add_argument("--with-ethernet", action="store_true", help="Enable Ethernet support.")
ethopts.add_argument("--with-etherbone", action="store_true", help="Enable Etherbone support.")
sdopts = parser.add_mutually_exclusive_group()
sdopts = target_group.add_mutually_exclusive_group()
sdopts.add_argument("--with-spi-sdcard", action="store_true", help="Enable SPI-mode SDCard support.")
sdopts.add_argument("--with-sdcard", action="store_true", help="Enable SDCard support.")
builder_args(parser)

13
litex_boards/targets/digilent_nexys4.py
View file

@ -207,16 +207,17 @@ class BaseSoC(SoCCore):
def main():
from litex.soc.integration.soc import LiteXSoCArgumentParser
parser = LiteXSoCArgumentParser(description="LiteX SoC on Nexys4")
parser.add_argument("--build", action="store_true", help="Build bitstream.")
parser.add_argument("--load", action="store_true", help="Load bitstream.")
parser.add_argument("--sys-clk-freq", default=75e6, help="System clock frequency.")
ethopts = parser.add_mutually_exclusive_group()
target_group = parser.add_argument_group(title="Target options")
target_group.add_argument("--build", action="store_true", help="Build bitstream.")
target_group.add_argument("--load", action="store_true", help="Load bitstream.")
target_group.add_argument("--sys-clk-freq", default=75e6, help="System clock frequency.")
ethopts = target_group.add_mutually_exclusive_group()
ethopts.add_argument("--with-ethernet", action="store_true", help="Enable Ethernet support.")
ethopts.add_argument("--with-etherbone", action="store_true", help="Enable Etherbone support.")
sdopts = parser.add_mutually_exclusive_group()
sdopts = target_group.add_mutually_exclusive_group()
sdopts.add_argument("--with-spi-sdcard", action="store_true", help="Enable SPI-mode SDCard support.")
sdopts.add_argument("--with-sdcard", action="store_true", help="Enable SDCard support.")
viopts = parser.add_mutually_exclusive_group()
viopts = target_group.add_mutually_exclusive_group()
viopts.add_argument("--with-video-terminal", action="store_true", help="Enable Video Terminal (VGA).")
viopts.add_argument("--with-video-framebuffer", action="store_true", help="Enable Video Framebuffer (VGA).")
builder_args(parser)

13
litex_boards/targets/digilent_nexys4ddr.py
View file

@ -105,16 +105,17 @@ class BaseSoC(SoCCore):
def main():
from litex.soc.integration.soc import LiteXSoCArgumentParser
parser = LiteXSoCArgumentParser(description="LiteX SoC on Nexys4DDR")
parser.add_argument("--build", action="store_true", help="Build bitstream.")
parser.add_argument("--load", action="store_true", help="Load bitstream.")
parser.add_argument("--sys-clk-freq", default=75e6, help="System clock frequency.")
ethopts = parser.add_mutually_exclusive_group()
target_group = parser.add_argument_group(title="Target options")
target_group.add_argument("--build", action="store_true", help="Build bitstream.")
target_group.add_argument("--load", action="store_true", help="Load bitstream.")
target_group.add_argument("--sys-clk-freq", default=75e6, help="System clock frequency.")
ethopts = target_group.add_mutually_exclusive_group()
ethopts.add_argument("--with-ethernet", action="store_true", help="Enable Ethernet support.")
ethopts.add_argument("--with-etherbone", action="store_true", help="Enable Etherbone support.")
sdopts = parser.add_mutually_exclusive_group()
sdopts = target_group.add_mutually_exclusive_group()
sdopts.add_argument("--with-spi-sdcard", action="store_true", help="Enable SPI-mode SDCard support.")
sdopts.add_argument("--with-sdcard", action="store_true", help="Enable SDCard support.")
viopts = parser.add_mutually_exclusive_group()
viopts = target_group.add_mutually_exclusive_group()
viopts.add_argument("--with-video-terminal", action="store_true", help="Enable Video Terminal (VGA).")
viopts.add_argument("--with-video-framebuffer", action="store_true", help="Enable Video Framebuffer (VGA).")
builder_args(parser)

23
litex_boards/targets/digilent_nexys_video.py
View file

@ -160,19 +160,20 @@ class BaseSoC(SoCCore):
def main():
from litex.soc.integration.soc import LiteXSoCArgumentParser
parser = LiteXSoCArgumentParser(description="LiteX SoC on Nexys Video")
parser.add_argument("--toolchain", default="vivado", help="FPGA toolchain (vivado or symbiflow).")
parser.add_argument("--build", action="store_true", help="Build bitstream.")
parser.add_argument("--load", action="store_true", help="Load bitstream.")
parser.add_argument("--sys-clk-freq", default=100e6, help="System clock frequency.")
parser.add_argument("--with-ethernet", action="store_true", help="Enable Ethernet support.")
sdopts = parser.add_mutually_exclusive_group()
target_group = parser.add_argument_group(title="Target options")
target_group.add_argument("--toolchain", default="vivado", help="FPGA toolchain (vivado or symbiflow).")
target_group.add_argument("--build", action="store_true", help="Build bitstream.")
target_group.add_argument("--load", action="store_true", help="Load bitstream.")
target_group.add_argument("--sys-clk-freq", default=100e6, help="System clock frequency.")
target_group.add_argument("--with-ethernet", action="store_true", help="Enable Ethernet support.")
sdopts = target_group.add_mutually_exclusive_group()
sdopts.add_argument("--with-spi-sdcard", action="store_true", help="Enable SPI-mode SDCard support.")
sdopts.add_argument("--with-sdcard", action="store_true", help="Enable SDCard support.")
parser.add_argument("--with-sata", action="store_true", help="Enable SATA support (over FMCRAID).")
parser.add_argument("--sata-gen", default="2", help="SATA Gen.", choices=["1", "2"])
parser.add_argument("--with-sata-pll-refclk", action="store_true", help="Generate SATA RefClk from PLL.")
parser.add_argument("--vadj", default="1.2V", help="FMC VADJ value.", choices=["1.2V", "1.8V", "2.5V", "3.3V"])
viopts = parser.add_mutually_exclusive_group()
target_group.add_argument("--with-sata", action="store_true", help="Enable SATA support (over FMCRAID).")
target_group.add_argument("--sata-gen", default="2", help="SATA Gen.", choices=["1", "2"])
target_group.add_argument("--with-sata-pll-refclk", action="store_true", help="Generate SATA RefClk from PLL.")
target_group.add_argument("--vadj", default="1.2V", help="FMC VADJ value.", choices=["1.2V", "1.8V", "2.5V", "3.3V"])
viopts = target_group.add_mutually_exclusive_group()
viopts.add_argument("--with-video-terminal", action="store_true", help="Enable Video Terminal (HDMI).")
viopts.add_argument("--with-video-framebuffer", action="store_true", help="Enable Video Framebuffer (HDMI).")
builder_args(parser)

9
litex_boards/targets/digilent_pynq_z1.py
View file

@ -101,10 +101,11 @@ class BaseSoC(SoCCore):
def main():
from litex.soc.integration.soc import LiteXSoCArgumentParser
parser = LiteXSoCArgumentParser(description="LiteX SoC on PYNQ Z1")
parser.add_argument("--build", action="store_true", help="Build bitstream.")
parser.add_argument("--load", action="store_true", help="Load bitstream.")
parser.add_argument("--sys-clk-freq", default=125e6, help="System clock frequency.")
parser.add_argument("--with-video-terminal", action="store_true", help="Enable Video Terminal (HDMI).")
target_group = parser.add_argument_group(title="Target options")
target_group.add_argument("--build", action="store_true", help="Build bitstream.")
target_group.add_argument("--load", action="store_true", help="Load bitstream.")
target_group.add_argument("--sys-clk-freq", default=125e6, help="System clock frequency.")
target_group.add_argument("--with-video-terminal", action="store_true", help="Enable Video Terminal (HDMI).")
builder_args(parser)
soc_core_args(parser)

7
litex_boards/targets/digilent_zedboard.py
View file

@ -153,9 +153,10 @@ class BaseSoC(SoCCore):
def main():
from litex.soc.integration.soc import LiteXSoCArgumentParser
parser = LiteXSoCArgumentParser(description="LiteX SoC on Zedboard")
parser.add_argument("--build", action="store_true", help="Build bitstream.")
parser.add_argument("--load", action="store_true", help="Load bitstream.")
parser.add_argument("--sys-clk-freq", default=100e6, help="System clock frequency.")
target_group = parser.add_argument_group(title="Target options")
target_group.add_argument("--build", action="store_true", help="Build bitstream.")
target_group.add_argument("--load", action="store_true", help="Load bitstream.")
target_group.add_argument("--sys-clk-freq", default=100e6, help="System clock frequency.")
builder_args(parser)
soc_core_args(parser)
vivado_build_args(parser)

7
litex_boards/targets/ebaz4205.py
View file

@ -68,9 +68,10 @@ class BaseSoC(SoCCore):
def main():
from litex.soc.integration.soc import LiteXSoCArgumentParser
parser = LiteXSoCArgumentParser(description="LiteX SoC on EBAZ4205")
parser.add_argument("--build", action="store_true", help="Build bitstream.")
parser.add_argument("--load", action="store_true", help="Load bitstream.")
parser.add_argument("--sys-clk-freq", default=100e6, help="System clock frequency.")
target_group = parser.add_argument_group(title="Target options")
target_group.add_argument("--build", action="store_true", help="Build bitstream.")
target_group.add_argument("--load", action="store_true", help="Load bitstream.")
target_group.add_argument("--sys-clk-freq", default=100e6, help="System clock frequency.")
builder_args(parser)
soc_core_args(parser)
vivado_build_args(parser)

15
litex_boards/targets/efinix_titanium_ti60_f225_dev_kit.py
View file

@ -73,13 +73,14 @@ class BaseSoC(SoCCore):
def main():
from litex.soc.integration.soc import LiteXSoCArgumentParser
parser = LiteXSoCArgumentParser(description="LiteX SoC on Efinix Titanium Ti60 F225 Dev Kit")
parser.add_argument("--build", action="store_true", help="Build bitstream.")
parser.add_argument("--load", action="store_true", help="Load bitstream.")
parser.add_argument("--flash", action="store_true", help="Flash bitstream.")
parser.add_argument("--sys-clk-freq", default=200e6, help="System clock frequency.")
parser.add_argument("--with-spi-flash", action="store_true", help="Enable SPI Flash (MMAPed).")
parser.add_argument("--with-hyperram", action="store_true", help="Enable HyperRAM.")
sdopts = parser.add_mutually_exclusive_group()
target_group = parser.add_argument_group(title="Target options")
target_group.add_argument("--build", action="store_true", help="Build bitstream.")
target_group.add_argument("--load", action="store_true", help="Load bitstream.")
target_group.add_argument("--flash", action="store_true", help="Flash bitstream.")
target_group.add_argument("--sys-clk-freq", default=200e6, help="System clock frequency.")
target_group.add_argument("--with-spi-flash", action="store_true", help="Enable SPI Flash (MMAPed).")
target_group.add_argument("--with-hyperram", action="store_true", help="Enable HyperRAM.")
sdopts = target_group.add_mutually_exclusive_group()
sdopts.add_argument("--with-spi-sdcard", action="store_true", help="Enable SPI-mode SDCard support.")
sdopts.add_argument("--with-sdcard", action="store_true", help="Enable SDCard support.")
builder_args(parser)

17
litex_boards/targets/efinix_trion_t120_bga576_dev_kit.py
View file

@ -340,16 +340,17 @@ calc_result = design.auto_calc_pll_clock("dram_pll", {"CLKOUT0_FREQ": "400.0"})
def main():
from litex.soc.integration.soc import LiteXSoCArgumentParser
parser = LiteXSoCArgumentParser(description="LiteX SoC on Efinix Trion T120 BGA576 Dev Kit")
parser.add_argument("--build", action="store_true", help="Build bitstream.")
parser.add_argument("--load", action="store_true", help="Load bitstream.")
parser.add_argument("--flash", action="store_true", help="Flash bitstream.")
parser.add_argument("--sys-clk-freq", default=75e6, help="System clock frequency.")
parser.add_argument("--with-spi-flash", action="store_true", help="Enable SPI Flash (MMAPed).")
ethopts = parser.add_mutually_exclusive_group()
target_group = parser.add_argument_group(title="Target options")
target_group.add_argument("--build", action="store_true", help="Build bitstream.")
target_group.add_argument("--load", action="store_true", help="Load bitstream.")
target_group.add_argument("--flash", action="store_true", help="Flash bitstream.")
target_group.add_argument("--sys-clk-freq", default=75e6, help="System clock frequency.")
target_group.add_argument("--with-spi-flash", action="store_true", help="Enable SPI Flash (MMAPed).")
ethopts = target_group.add_mutually_exclusive_group()
ethopts.add_argument("--with-ethernet", action="store_true", help="Enable Ethernet support.")
ethopts.add_argument("--with-etherbone", action="store_true", help="Enable Etherbone support.")
parser.add_argument("--eth-ip", default="192.168.1.50", type=str, help="Ethernet/Etherbone IP address.")
parser.add_argument("--eth-phy", default=0, type=int, help="Ethernet PHY: 0 (default) or 1.")
target_group.add_argument("--eth-ip", default="192.168.1.50", type=str, help="Ethernet/Etherbone IP address.")
target_group.add_argument("--eth-phy", default=0, type=int, help="Ethernet PHY: 0 (default) or 1.")
builder_args(parser)
soc_core_args(parser)
args = parser.parse_args()

11
litex_boards/targets/efinix_trion_t20_bga256_dev_kit.py
View file

@ -69,11 +69,12 @@ class BaseSoC(SoCCore):
def main():
from litex.soc.integration.soc import LiteXSoCArgumentParser
parser = LiteXSoCArgumentParser(description="LiteX SoC on Efinix Trion T20 BGA256 Dev Kit")
parser.add_argument("--build", action="store_true", help="Build bitstream.")
parser.add_argument("--load", action="store_true", help="Load bitstream.")
parser.add_argument("--flash", action="store_true", help="Flash bitstream.")
parser.add_argument("--sys-clk-freq", default=100e6, help="System clock frequency.")
parser.add_argument("--with-spi-flash", action="store_true", help="Enable SPI Flash (MMAPed).")
target_group = parser.add_argument_group(title="Target options")
target_group.add_argument("--build", action="store_true", help="Build bitstream.")
target_group.add_argument("--load", action="store_true", help="Load bitstream.")
target_group.add_argument("--flash", action="store_true", help="Flash bitstream.")
target_group.add_argument("--sys-clk-freq", default=100e6, help="System clock frequency.")
target_group.add_argument("--with-spi-flash", action="store_true", help="Enable SPI Flash (MMAPed).")
builder_args(parser)
soc_core_args(parser)
args = parser.parse_args()

9
litex_boards/targets/efinix_trion_t20_mipi_dev_kit.py
View file

@ -67,10 +67,11 @@ class BaseSoC(SoCCore):
def main():
from litex.soc.integration.soc import LiteXSoCArgumentParser
parser = LiteXSoCArgumentParser(description="LiteX SoC on Efinix Trion T20 MIPI Dev Kit")
parser.add_argument("--build", action="store_true", help="Build bitstream.")
parser.add_argument("--load", action="store_true", help="Load bitstream.")
parser.add_argument("--sys-clk-freq", default=100e6, help="System clock frequency.")
parser.add_argument("--with-spi-flash", action="store_true", help="Enable SPI Flash (MMAPed).")
target_group = parser.add_argument_group(title="Target options")
target_group.add_argument("--build", action="store_true", help="Build bitstream.")
target_group.add_argument("--load", action="store_true", help="Load bitstream.")
target_group.add_argument("--sys-clk-freq", default=100e6, help="System clock frequency.")
target_group.add_argument("--with-spi-flash", action="store_true", help="Enable SPI Flash (MMAPed).")
builder_args(parser)
soc_core_args(parser)
args = parser.parse_args()

11
litex_boards/targets/efinix_xyloni_dev_kit.py
View file

@ -85,11 +85,12 @@ class BaseSoC(SoCCore):
def main():
from litex.soc.integration.soc import LiteXSoCArgumentParser
parser = LiteXSoCArgumentParser(description="LiteX SoC on Efinix Xyloni Dev Kit")
parser.add_argument("--build", action="store_true", help="Build bitstream.")
parser.add_argument("--load", action="store_true", help="Load bitstream.")
parser.add_argument("--flash", action="store_true", help="Flash Bitstream.")
parser.add_argument("--sys-clk-freq", default=33.333e6, help="System clock frequency.")
parser.add_argument("--bios-flash-offset", default="0x40000", help="BIOS offset in SPI Flash.")
target_group = parser.add_argument_group(title="Target options")
target_group.add_argument("--build", action="store_true", help="Build bitstream.")
target_group.add_argument("--load", action="store_true", help="Load bitstream.")
target_group.add_argument("--flash", action="store_true", help="Flash Bitstream.")
target_group.add_argument("--sys-clk-freq", default=33.333e6, help="System clock frequency.")
target_group.add_argument("--bios-flash-offset", default="0x40000", help="BIOS offset in SPI Flash.")
builder_args(parser)
soc_core_args(parser)

11
litex_boards/targets/ego1.py
View file

@ -63,11 +63,12 @@ class BaseSoC(SoCCore):
def main():
from litex.soc.integration.soc import LiteXSoCArgumentParser
parser = LiteXSoCArgumentParser(description="LiteX SoC on EGO1")
parser.add_argument("--build", action="store_true", help="Build bitstream.")
parser.add_argument("--load", action="store_true", help="Load bitstream.")
parser.add_argument("--flash", action="store_true", help="Flash bitstream.")
parser.add_argument("--with-video-terminal", action="store_true", help="Enable Video Terminal.")
parser.add_argument("--sys-clk-freq", default=100e6, help="System clock frequency.")
target_group = parser.add_argument_group(title="Target options")
target_group.add_argument("--build", action="store_true", help="Build bitstream.")
target_group.add_argument("--load", action="store_true", help="Load bitstream.")
target_group.add_argument("--flash", action="store_true", help="Flash bitstream.")
target_group.add_argument("--with-video-terminal", action="store_true", help="Enable Video Terminal.")
target_group.add_argument("--sys-clk-freq", default=100e6, help="System clock frequency.")
builder_args(parser)
soc_core_args(parser)

7
litex_boards/targets/enclustra_mercury_kx2.py
View file

@ -77,9 +77,10 @@ class BaseSoC(SoCCore):
def main():
from litex.soc.integration.soc import LiteXSoCArgumentParser
parser = LiteXSoCArgumentParser(description="LiteX SoC on KX2")
parser.add_argument("--build", action="store_true", help="Build bitstream.")
parser.add_argument("--load", action="store_true", help="Load bitstream.")
parser.add_argument("--sys-clk-freq", default=100e6, help="System clock frequency.")
target_group = parser.add_argument_group(title="Target options")
target_group.add_argument("--build", action="store_true", help="Build bitstream.")
target_group.add_argument("--load", action="store_true", help="Load bitstream.")
target_group.add_argument("--sys-clk-freq", default=100e6, help="System clock frequency.")
builder_args(parser)
soc_core_args(parser)
args = parser.parse_args()

7
litex_boards/targets/enclustra_mercury_xu5.py
View file

@ -85,9 +85,10 @@ class BaseSoC(SoCCore):
def main():
from litex.soc.integration.soc import LiteXSoCArgumentParser
parser = LiteXSoCArgumentParser(description="LiteX SoC on Mercury XU5")
parser.add_argument("--build", action="store_true", help="Build bitstream.")
parser.add_argument("--load", action="store_true", help="Load bitstream.")
parser.add_argument("--sys-clk-freq", default=125e6, help="System clock frequency.")
target_group = parser.add_argument_group(title="Target options")
target_group.add_argument("--build", action="store_true", help="Build bitstream.")
target_group.add_argument("--load", action="store_true", help="Load bitstream.")
target_group.add_argument("--sys-clk-freq", default=125e6, help="System clock frequency.")
builder_args(parser)
soc_core_args(parser)
args = parser.parse_args()

13
litex_boards/targets/fairwaves_xtrx.py
View file

@ -105,12 +105,13 @@ class BaseSoC(SoCCore):
def main():
from litex.soc.integration.soc import LiteXSoCArgumentParser
parser = LiteXSoCArgumentParser(description="LiteX SoC on Fairwaves XTRX")
parser.add_argument("--build", action="store_true", help="Build bitstream.")
parser.add_argument("--load", action="store_true", help="Load bitstream.")
parser.add_argument("--flash", action="store_true", help="Flash bitstream.")
parser.add_argument("--sys-clk-freq", default=125e6, help="System clock frequency.")
parser.add_argument("--with-pcie", action="store_true", help="Enable PCIe support.")
parser.add_argument("--driver", action="store_true", help="Generate PCIe driver.")
target_group = parser.add_argument_group(title="Target options")
target_group.add_argument("--build", action="store_true", help="Build bitstream.")
target_group.add_argument("--load", action="store_true", help="Load bitstream.")
target_group.add_argument("--flash", action="store_true", help="Flash bitstream.")
target_group.add_argument("--sys-clk-freq", default=125e6, help="System clock frequency.")
target_group.add_argument("--with-pcie", action="store_true", help="Enable PCIe support.")
target_group.add_argument("--driver", action="store_true", help="Generate PCIe driver.")
builder_args(parser)
soc_core_args(parser)
args = parser.parse_args()

13
litex_boards/targets/fpc_iii.py
View file

@ -130,14 +130,15 @@ class BaseSoC(SoCCore):
def main():
from litex.soc.integration.soc import LiteXSoCArgumentParser
parser = LiteXSoCArgumentParser(description="LiteX SoC on FPC-III")
parser.add_argument("--build", action="store_true", help="Build bitstream.")
parser.add_argument("--load", action="store_true", help="Load bitstream.")
parser.add_argument("--toolchain", default="trellis", help="Gateware toolchain to use (trellis or diamond).")
parser.add_argument("--sys-clk-freq", default=80e6, help="System clock frequency.")
ethopts = parser.add_mutually_exclusive_group()
target_group = parser.add_argument_group(title="Target options")
target_group.add_argument("--build", action="store_true", help="Build bitstream.")
target_group.add_argument("--load", action="store_true", help="Load bitstream.")
target_group.add_argument("--toolchain", default="trellis", help="Gateware toolchain to use (trellis or diamond).")
target_group.add_argument("--sys-clk-freq", default=80e6, help="System clock frequency.")
ethopts = target_group.add_mutually_exclusive_group()
ethopts.add_argument("--with-ethernet", action="store_true", help="Enable Ethernet support.")
ethopts.add_argument("--with-etherbone", action="store_true", help="Enable Etherbone support.")
sdopts = parser.add_mutually_exclusive_group()
sdopts = target_group.add_mutually_exclusive_group()
sdopts.add_argument("--with-spi-sdcard", action="store_true", help="Enable SPI-mode SDCard support.")
sdopts.add_argument("--with-sdcard", action="store_true", help="Enable SDCard support.")
builder_args(parser)

27
litex_boards/targets/gsd_butterstick.py
View file

@ -154,23 +154,24 @@ class BaseSoC(SoCCore):
def main():
from litex.soc.integration.soc import LiteXSoCArgumentParser
parser = LiteXSoCArgumentParser(description="LiteX SoC on ButterStick")
parser.add_argument("--build", action="store_true", help="Build bitstream.")
parser.add_argument("--load", action="store_true", help="Load bitstream.")
parser.add_argument("--toolchain", default="trellis", help="FPGA toolchain (trellis or diamond).")
parser.add_argument("--sys-clk-freq", default=75e6, help="System clock frequency.")
parser.add_argument("--revision", default="1.0", help="Board Revision (1.0).")
parser.add_argument("--device", default="85F", help="ECP5 device (25F, 45F, 85F).")
parser.add_argument("--sdram-device", default="MT41K64M16", help="SDRAM device (MT41K64M16, MT41K128M16, MT41K256M16 or MT41K512M16).")
ethopts = parser.add_mutually_exclusive_group()
target_group = parser.add_argument_group(title="Target options")
target_group.add_argument("--build", action="store_true", help="Build bitstream.")
target_group.add_argument("--load", action="store_true", help="Load bitstream.")
target_group.add_argument("--toolchain", default="trellis", help="FPGA toolchain (trellis or diamond).")
target_group.add_argument("--sys-clk-freq", default=75e6, help="System clock frequency.")
target_group.add_argument("--revision", default="1.0", help="Board Revision (1.0).")
target_group.add_argument("--device", default="85F", help="ECP5 device (25F, 45F, 85F).")
target_group.add_argument("--sdram-device", default="MT41K64M16", help="SDRAM device (MT41K64M16, MT41K128M16, MT41K256M16 or MT41K512M16).")
ethopts = target_group.add_mutually_exclusive_group()
ethopts.add_argument("--with-ethernet", action="store_true", help="Add Ethernet.")
ethopts.add_argument("--with-etherbone", action="store_true", help="Add EtherBone.")
parser.add_argument("--eth-ip", default="192.168.1.50", help="Ethernet/Etherbone IP address.")
parser.add_argument("--eth-dynamic-ip", action="store_true", help="Enable dynamic Ethernet IP addresses setting.")
parser.add_argument("--with-spi-flash", action="store_true", help="Enable SPI Flash (MMAPed).")
sdopts = parser.add_mutually_exclusive_group()
target_group.add_argument("--eth-ip", default="192.168.1.50", help="Ethernet/Etherbone IP address.")
target_group.add_argument("--eth-dynamic-ip", action="store_true", help="Enable dynamic Ethernet IP addresses setting.")
target_group.add_argument("--with-spi-flash", action="store_true", help="Enable SPI Flash (MMAPed).")
sdopts = target_group.add_mutually_exclusive_group()
sdopts.add_argument("--with-spi-sdcard", action="store_true", help="Enable SPI-mode SDCard support.")
sdopts.add_argument("--with-sdcard", action="store_true", help="Enable SDCard support.")
parser.add_argument("--with-syzygy-gpio",action="store_true", help="Enable GPIOs through SYZYGY Breakout on Port-A.")
target_group.add_argument("--with-syzygy-gpio",action="store_true", help="Enable GPIOs through SYZYGY Breakout on Port-A.")
builder_args(parser)
soc_core_args(parser)
trellis_args(parser)

17
litex_boards/targets/gsd_orangecrab.py
View file

@ -206,14 +206,15 @@ class BaseSoC(SoCCore):
def main():
from litex.soc.integration.soc import LiteXSoCArgumentParser
parser = LiteXSoCArgumentParser(description="LiteX SoC on OrangeCrab")
parser.add_argument("--build", action="store_true", help="Build bitstream.")
parser.add_argument("--load", action="store_true", help="Load bitstream.")
parser.add_argument("--toolchain", default="trellis", help="FPGA toolchain (trellis or diamond).")
parser.add_argument("--sys-clk-freq", default=48e6, help="System clock frequency.")
parser.add_argument("--revision", default="0.2", help="Board Revision (0.1 or 0.2).")
parser.add_argument("--device", default="25F", help="ECP5 device (25F, 45F or 85F).")
parser.add_argument("--sdram-device", default="MT41K64M16", help="SDRAM device (MT41K64M16, MT41K128M16, MT41K256M16 or MT41K512M16).")
parser.add_argument("--with-spi-sdcard", action="store_true", help="Enable SPI-mode SDCard support.")
target_group = parser.add_argument_group(title="Target options")
target_group.add_argument("--build", action="store_true", help="Build bitstream.")
target_group.add_argument("--load", action="store_true", help="Load bitstream.")
target_group.add_argument("--toolchain", default="trellis", help="FPGA toolchain (trellis or diamond).")
target_group.add_argument("--sys-clk-freq", default=48e6, help="System clock frequency.")
target_group.add_argument("--revision", default="0.2", help="Board Revision (0.1 or 0.2).")
target_group.add_argument("--device", default="25F", help="ECP5 device (25F, 45F or 85F).")
target_group.add_argument("--sdram-device", default="MT41K64M16", help="SDRAM device (MT41K64M16, MT41K128M16, MT41K256M16 or MT41K512M16).")
target_group.add_argument("--with-spi-sdcard", action="store_true", help="Enable SPI-mode SDCard support.")
builder_args(parser)
soc_core_args(parser)
trellis_args(parser)

7
litex_boards/targets/hackaday_hadbadge.py
View file

@ -78,9 +78,10 @@ class BaseSoC(SoCCore):
def main():
from litex.soc.integration.soc import LiteXSoCArgumentParser
parser = LiteXSoCArgumentParser(description="LiteX SoC on Hackaday Badge")
parser.add_argument("--build", action="store_true", help="Build bitstream.")
parser.add_argument("--toolchain", default="trellis", help="FPGA toolchain (trellis or diamond).")
parser.add_argument("--sys-clk-freq", default=48e6, help="System clock frequency.")
target_group = parser.add_argument_group(title="Target options")
target_group.add_argument("--build", action="store_true", help="Build bitstream.")
target_group.add_argument("--toolchain", default="trellis", help="FPGA toolchain (trellis or diamond).")
target_group.add_argument("--sys-clk-freq", default=48e6, help="System clock frequency.")
builder_args(parser)
soc_core_args(parser)
trellis_args(parser)

11
litex_boards/targets/jungle_electronics_fireant.py
View file

@ -101,11 +101,12 @@ class BaseSoC(SoCCore):
def main():
from litex.soc.integration.soc import LiteXSoCArgumentParser
parser = LiteXSoCArgumentParser(description="LiteX SoC on Jungle Electronics FireAnt")
parser.add_argument("--build", action="store_true", help="Build bitstream.")
parser.add_argument("--load", action="store_true", help="Load bitstream.")
parser.add_argument("--flash", action="store_true", help="Flash Bitstream.")
parser.add_argument("--sys-clk-freq", default=33.333e6, help="System clock frequency.")
parser.add_argument("--bios-flash-offset", default="0x40000", help="BIOS offset in SPI Flash.")
target_group = parser.add_argument_group(title="Target options")
target_group.add_argument("--build", action="store_true", help="Build bitstream.")
target_group.add_argument("--load", action="store_true", help="Load bitstream.")
target_group.add_argument("--flash", action="store_true", help="Flash Bitstream.")
target_group.add_argument("--sys-clk-freq", default=33.333e6, help="System clock frequency.")
target_group.add_argument("--bios-flash-offset", default="0x40000", help="BIOS offset in SPI Flash.")
builder_args(parser)
soc_core_args(parser)

9
litex_boards/targets/kosagi_fomu.py
View file

@ -164,10 +164,11 @@ def flash(build_dir, build_name, bios_flash_offset):
def main():
from litex.soc.integration.soc import LiteXSoCArgumentParser
parser = LiteXSoCArgumentParser(description="LiteX SoC on Fomu")
parser.add_argument("--build", action="store_true", help="Build bitstream.")
parser.add_argument("--sys-clk-freq", default=12e6, help="System clock frequency.")
parser.add_argument("--bios-flash-offset", default="0x20000", help="BIOS offset in SPI Flash.")
parser.add_argument("--flash", action="store_true", help="Flash Bitstream.")
target_group = parser.add_argument_group(title="Target options")
target_group.add_argument("--build", action="store_true", help="Build bitstream.")
target_group.add_argument("--sys-clk-freq", default=12e6, help="System clock frequency.")
target_group.add_argument("--bios-flash-offset", default="0x20000", help="BIOS offset in SPI Flash.")
target_group.add_argument("--flash", action="store_true", help="Flash Bitstream.")
builder_args(parser)
soc_core_args(parser)
args = parser.parse_args()

17
litex_boards/targets/kosagi_netv2.py
View file

@ -108,14 +108,15 @@ class BaseSoC(SoCCore):
def main():
from litex.soc.integration.soc import LiteXSoCArgumentParser
parser = LiteXSoCArgumentParser(description="LiteX SoC on NeTV2")
parser.add_argument("--build", action="store_true", help="Build bitstream.")
parser.add_argument("--load", action="store_true", help="Load bitstream.")
parser.add_argument("--variant", default="a7-35", help="Board variant (a7-35 or a7-100).")
parser.add_argument("--sys-clk-freq", default=100e6, help="System clock frequency.")
parser.add_argument("--with-ethernet", action="store_true", help="Enable Ethernet support.")
parser.add_argument("--with-pcie", action="store_true", help="Enable PCIe support.")
parser.add_argument("--driver", action="store_true", help="Generate PCIe driver.")
sdopts = parser.add_mutually_exclusive_group()
target_group = parser.add_argument_group(title="Target options")
target_group.add_argument("--build", action="store_true", help="Build bitstream.")
target_group.add_argument("--load", action="store_true", help="Load bitstream.")
target_group.add_argument("--variant", default="a7-35", help="Board variant (a7-35 or a7-100).")
target_group.add_argument("--sys-clk-freq", default=100e6, help="System clock frequency.")
target_group.add_argument("--with-ethernet", action="store_true", help="Enable Ethernet support.")
target_group.add_argument("--with-pcie", action="store_true", help="Enable PCIe support.")
target_group.add_argument("--driver", action="store_true", help="Generate PCIe driver.")
sdopts = target_group.add_mutually_exclusive_group()
sdopts.add_argument("--with-spi-sdcard", action="store_true", help="Enable SPI-mode SDCard support.")
sdopts.add_argument("--with-sdcard", action="store_true", help="Enable SDCard support.")

15
litex_boards/targets/krtkl_snickerdoodle.py
View file

@ -113,13 +113,14 @@ class BaseSoC(SoCCore):
def main():
from litex.soc.integration.soc import LiteXSoCArgumentParser
parser = LiteXSoCArgumentParser(description="LiteX SoC on Snickerdoodle")
parser.add_argument("--build", action="store_true", help="Build bitstream.")
parser.add_argument("--load", action="store_true", help="Load bitstream.")
parser.add_argument("--variant", default="z7-10", help="Board variant (z7-10 or z7-20).")
parser.add_argument("--ext-clk-freq", default=10e6, type=float, help="External Clock Frequency.")
parser.add_argument("--sys-clk-freq", default=100e6, type=float, help="System clock frequency.")
parser.add_argument("--xci-file", help="XCI file for PS7 configuration.")
parser.add_argument("--target", help="Vivado programmer target.")
target_group = parser.add_argument_group(title="Target options")
target_group.add_argument("--build", action="store_true", help="Build bitstream.")
target_group.add_argument("--load", action="store_true", help="Load bitstream.")
target_group.add_argument("--variant", default="z7-10", help="Board variant (z7-10 or z7-20).")
target_group.add_argument("--ext-clk-freq", default=10e6, type=float, help="External Clock Frequency.")
target_group.add_argument("--sys-clk-freq", default=100e6, type=float, help="System clock frequency.")
target_group.add_argument("--xci-file", help="XCI file for PS7 configuration.")
target_group.add_argument("--target", help="Vivado programmer target.")
builder_args(parser)
soc_core_args(parser)
vivado_build_args(parser)

17
litex_boards/targets/lambdaconcept_ecpix5.py
View file

@ -225,16 +225,17 @@ class BaseSoC(SoCCore):
def main():
from litex.soc.integration.soc import LiteXSoCArgumentParser
parser = LiteXSoCArgumentParser(description="LiteX SoC on ECPIX-5")
parser.add_argument("--build", action="store_true", help="Build bitstream.")
parser.add_argument("--load", action="store_true", help="Load bitstream.")
parser.add_argument("--flash", action="store_true", help="Flash bitstream to SPI Flash.")
parser.add_argument("--device", default="85F", help="ECP5 device (45F or 85F).")
parser.add_argument("--sys-clk-freq", default=75e6, help="System clock frequency.")
parser.add_argument("--with-sdcard", action="store_true", help="Enable SDCard support.")
ethopts = parser.add_mutually_exclusive_group()
target_group = parser.add_argument_group(title="Target options")
target_group.add_argument("--build", action="store_true", help="Build bitstream.")
target_group.add_argument("--load", action="store_true", help="Load bitstream.")
target_group.add_argument("--flash", action="store_true", help="Flash bitstream to SPI Flash.")
target_group.add_argument("--device", default="85F", help="ECP5 device (45F or 85F).")
target_group.add_argument("--sys-clk-freq", default=75e6, help="System clock frequency.")
target_group.add_argument("--with-sdcard", action="store_true", help="Enable SDCard support.")
ethopts = target_group.add_mutually_exclusive_group()
ethopts.add_argument("--with-ethernet", action="store_true", help="Enable Ethernet support.")
ethopts.add_argument("--with-etherbone", action="store_true", help="Enable Etherbone support.")
viopts = parser.add_mutually_exclusive_group()
viopts = target_group.add_mutually_exclusive_group()
viopts.add_argument("--with-video-terminal", action="store_true", help="Enable Video Terminal (HDMI).")
viopts.add_argument("--with-video-framebuffer", action="store_true", help="Enable Video Framebuffer (HDMI).")

15
litex_boards/targets/lattice_crosslink_nx_evn.py
View file

@ -97,13 +97,14 @@ class BaseSoC(SoCCore):
def main():
from litex.soc.integration.soc import LiteXSoCArgumentParser
parser = LiteXSoCArgumentParser(description="LiteX SoC on Crosslink-NX Eval Board")
parser.add_argument("--build", action="store_true", help="Build bitstream.")
parser.add_argument("--load", action="store_true", help="Load bitstream.")
parser.add_argument("--toolchain", default="radiant", help="FPGA toolchain (radiant or prjoxide).")
parser.add_argument("--device", default="LIFCL-40-9BG400C", help="FPGA device (LIFCL-40-9BG400C or LIFCL-40-8BG400CES).")
parser.add_argument("--sys-clk-freq", default=75e6, help="System clock frequency.")
parser.add_argument("--serial", default="serial", help="UART Pins (serial (requires R15 and R17 to be soldered) or serial_pmod[0-2]).")
parser.add_argument("--prog-target", default="direct", help="Programming Target (direct or flash).")
target_group = parser.add_argument_group(title="Target options")
target_group.add_argument("--build", action="store_true", help="Build bitstream.")
target_group.add_argument("--load", action="store_true", help="Load bitstream.")
target_group.add_argument("--toolchain", default="radiant", help="FPGA toolchain (radiant or prjoxide).")
target_group.add_argument("--device", default="LIFCL-40-9BG400C", help="FPGA device (LIFCL-40-9BG400C or LIFCL-40-8BG400CES).")
target_group.add_argument("--sys-clk-freq", default=75e6, help="System clock frequency.")
target_group.add_argument("--serial", default="serial", help="UART Pins (serial (requires R15 and R17 to be soldered) or serial_pmod[0-2]).")
target_group.add_argument("--prog-target", default="direct", help="Programming Target (direct or flash).")
builder_args(parser)
soc_core_args(parser)
oxide_args(parser)

13
litex_boards/targets/lattice_crosslink_nx_vip.py
View file

@ -105,12 +105,13 @@ class BaseSoC(SoCCore):
def main():
from litex.soc.integration.soc import LiteXSoCArgumentParser
parser = LiteXSoCArgumentParser(description="LiteX SoC on Crosslink-NX VIP Board")
parser.add_argument("--build", action="store_true", help="Build bitstream.")
parser.add_argument("--load", action="store_true", help="Load bitstream.")
parser.add_argument("--toolchain", default="radiant", help="FPGA toolchain (radiant or prjoxide).")
parser.add_argument("--sys-clk-freq", default=75e6, help="System clock frequency.")
parser.add_argument("--with-hyperram", default="none", help="Enable use of HyperRAM chip (none, 0 or 1).")
parser.add_argument("--prog-target", default="direct", help="Programming Target (direct or flash).")
target_group = parser.add_argument_group(title="Target options")
target_group.add_argument("--build", action="store_true", help="Build bitstream.")
target_group.add_argument("--load", action="store_true", help="Load bitstream.")
target_group.add_argument("--toolchain", default="radiant", help="FPGA toolchain (radiant or prjoxide).")
target_group.add_argument("--sys-clk-freq", default=75e6, help="System clock frequency.")
target_group.add_argument("--with-hyperram", default="none", help="Enable use of HyperRAM chip (none, 0 or 1).")
target_group.add_argument("--prog-target", default="direct", help="Programming Target (direct or flash).")
builder_args(parser)
soc_core_args(parser)
oxide_args(parser)

11
litex_boards/targets/lattice_ecp5_evn.py
View file

@ -66,11 +66,12 @@ class BaseSoC(SoCCore):
def main():
from litex.soc.integration.soc import LiteXSoCArgumentParser
parser = LiteXSoCArgumentParser(description="LiteX SoC on ECP5 Evaluation Board")
parser.add_argument("--build", action="store_true", help="Build bitstream.")
parser.add_argument("--load", action="store_true", help="Load bitstream.")
parser.add_argument("--toolchain", default="trellis", help="FPGA toolchain (trellis or diamond).")
parser.add_argument("--sys-clk-freq", default=60e6, help="System clock frequency.")
parser.add_argument("--x5-clk-freq", type=int, help="Use X5 oscillator as system clock at the specified frequency.")
target_group = parser.add_argument_group(title="Target options")
target_group.add_argument("--build", action="store_true", help="Build bitstream.")
target_group.add_argument("--load", action="store_true", help="Load bitstream.")
target_group.add_argument("--toolchain", default="trellis", help="FPGA toolchain (trellis or diamond).")
target_group.add_argument("--sys-clk-freq", default=60e6, help="System clock frequency.")
target_group.add_argument("--x5-clk-freq", type=int, help="Use X5 oscillator as system clock at the specified frequency.")
builder_args(parser)
soc_core_args(parser)
args = parser.parse_args()

9
litex_boards/targets/lattice_ecp5_vip.py
View file

@ -197,10 +197,11 @@ class BaseSoC(SoCCore):
def main():
from litex.soc.integration.soc import LiteXSoCArgumentParser
parser = LiteXSoCArgumentParser(description="LiteX SoC on ECP5 Evaluation Board")
parser.add_argument("--build", action="store_true", help="Build bitstream")
parser.add_argument("--load", action="store_true", help="Load bitstream")
parser.add_argument("--toolchain", default="trellis", help="FPGA toolchain: trellis (default) or diamond")
parser.add_argument("--sys-clk-freq", default=60e6, help="System clock frequency (default: 60MHz)")
target_group = parser.add_argument_group(title="Target options")
target_group.add_argument("--build", action="store_true", help="Build bitstream")
target_group.add_argument("--load", action="store_true", help="Load bitstream")
target_group.add_argument("--toolchain", default="trellis", help="FPGA toolchain: trellis (default) or diamond")
target_group.add_argument("--sys-clk-freq", default=60e6, help="System clock frequency (default: 60MHz)")
builder_args(parser)
soc_core_args(parser)
args = parser.parse_args()

9
litex_boards/targets/lattice_ice40up5k_evn.py
View file

@ -132,10 +132,11 @@ def flash(bios_flash_offset, target="lattice_ice40up5k_evn"):
def main():
from litex.soc.integration.soc import LiteXSoCArgumentParser
parser = LiteXSoCArgumentParser(description="LiteX SoC on Lattice iCE40UP5k EVN breakout board")
parser.add_argument("--build", action="store_true", help="Build bitstream.")
parser.add_argument("--sys-clk-freq", default=12e6, help="System clock frequency.")
parser.add_argument("--bios-flash-offset", default="0x20000", help="BIOS offset in SPI Flash.")
parser.add_argument("--flash", action="store_true", help="Flash Bitstream.")
target_group = parser.add_argument_group(title="Target options")
target_group.add_argument("--build", action="store_true", help="Build bitstream.")
target_group.add_argument("--sys-clk-freq", default=12e6, help="System clock frequency.")
target_group.add_argument("--bios-flash-offset", default="0x20000", help="BIOS offset in SPI Flash.")
target_group.add_argument("--flash", action="store_true", help="Flash Bitstream.")
builder_args(parser)
soc_core_args(parser)
args = parser.parse_args()

17
litex_boards/targets/lattice_versa_ecp5.py
View file

@ -128,16 +128,17 @@ class BaseSoC(SoCCore):
def main():
from litex.soc.integration.soc import LiteXSoCArgumentParser
parser = LiteXSoCArgumentParser(description="LiteX SoC on Versa ECP5")
parser.add_argument("--build", action="store_true", help="Build bitstream.")
parser.add_argument("--load", action="store_true", help="Load bitstream.")
parser.add_argument("--toolchain", default="trellis", help="FPGA toolchain (trellis or diamond).")
parser.add_argument("--sys-clk-freq", default=75e6, help="System clock frequency.")
parser.add_argument("--device", default="LFE5UM5G", help="FPGA device (LFE5UM5G or LFE5UM).")
ethopts = parser.add_mutually_exclusive_group()
target_group = parser.add_argument_group(title="Target options")
target_group.add_argument("--build", action="store_true", help="Build bitstream.")
target_group.add_argument("--load", action="store_true", help="Load bitstream.")
target_group.add_argument("--toolchain", default="trellis", help="FPGA toolchain (trellis or diamond).")
target_group.add_argument("--sys-clk-freq", default=75e6, help="System clock frequency.")
target_group.add_argument("--device", default="LFE5UM5G", help="FPGA device (LFE5UM5G or LFE5UM).")
ethopts = target_group.add_mutually_exclusive_group()
ethopts.add_argument("--with-ethernet", action="store_true", help="Enable Ethernet support.")
ethopts.add_argument("--with-etherbone", action="store_true", help="Enable Etherbone support.")
parser.add_argument("--eth-ip", default="192.168.1.50", type=str, help="Ethernet/Etherbone IP address.")
parser.add_argument("--eth-phy", default=0, type=int, help="Ethernet PHY (0 or 1).")
target_group.add_argument("--eth-ip", default="192.168.1.50", type=str, help="Ethernet/Etherbone IP address.")
target_group.add_argument("--eth-phy", default=0, type=int, help="Ethernet PHY (0 or 1).")
builder_args(parser)
soc_core_args(parser)
trellis_args(parser)

11
litex_boards/targets/linsn_rv901t.py
View file

@ -91,13 +91,14 @@ class BaseSoC(SoCCore):
def main():
from litex.soc.integration.soc import LiteXSoCArgumentParser
parser = LiteXSoCArgumentParser(description="LiteX SoC on Linsn RV901T")
parser.add_argument("--build", action="store_true", help="Build bitstream.")
parser.add_argument("--load", action="store_true", help="Load bitstream.")
parser.add_argument("--sys-clk-freq", default=75e6, help="System clock frequency.")
ethopts = parser.add_mutually_exclusive_group()
target_group = parser.add_argument_group(title="Target options")
target_group.add_argument("--build", action="store_true", help="Build bitstream.")
target_group.add_argument("--load", action="store_true", help="Load bitstream.")
target_group.add_argument("--sys-clk-freq", default=75e6, help="System clock frequency.")
ethopts = target_group.add_mutually_exclusive_group()
ethopts.add_argument("--with-ethernet", action="store_true", help="Enable Ethernet support.")
ethopts.add_argument("--with-etherbone", action="store_true", help="Enable Etherbone support.")
parser.add_argument("--eth-phy", default=0, type=int, help="Ethernet PHY (0 or 1).")
target_group.add_argument("--eth-phy", default=0, type=int, help="Ethernet PHY (0 or 1).")
builder_args(parser)
soc_core_args(parser)
args = parser.parse_args()

21
litex_boards/targets/litex_acorn_baseboard.py
View file

@ -123,21 +123,22 @@ class BaseSoC(SoCCore):
def main():
from litex.soc.integration.soc import LiteXSoCArgumentParser
parser = LiteXSoCArgumentParser(description="LiteX SoC on LiteX Acorn Baseboard")
parser.add_argument("--build", action="store_true", help="Build bitstream.")
parser.add_argument("--load", action="store_true", help="Load bitstream.")
parser.add_argument("--flash", action="store_true", help="Flash bitstream to SPI Flash.")
parser.add_argument("--sys-clk-freq", default=75e6, help="System clock frequency.")
ethopts = parser.add_mutually_exclusive_group()
target_group = parser.add_argument_group(title="Target options")
target_group.add_argument("--build", action="store_true", help="Build bitstream.")
target_group.add_argument("--load", action="store_true", help="Load bitstream.")
target_group.add_argument("--flash", action="store_true", help="Flash bitstream to SPI Flash.")
target_group.add_argument("--sys-clk-freq", default=75e6, help="System clock frequency.")
ethopts = target_group.add_mutually_exclusive_group()
ethopts.add_argument("--with-ethernet", action="store_true", help="Enable Ethernet support.")
ethopts.add_argument("--with-etherbone", action="store_true", help="Enable Etherbone support.")
sdopts = parser.add_mutually_exclusive_group()
sdopts = target_group.add_mutually_exclusive_group()
sdopts.add_argument("--with-spi-sdcard", action="store_true", help="Enable SPI-mode SDCard support.")
sdopts.add_argument("--with-sdcard", action="store_true", help="Enable SDCard support.")
viopts = parser.add_mutually_exclusive_group()
viopts = target_group.add_mutually_exclusive_group()
viopts.add_argument("--with-video-terminal", action="store_true", help="Enable Video Terminal (HDMI).")
parser.add_argument("--with-spi-flash", action="store_true", help="Enable SPI Flash (MMAPed).")
parser.add_argument("--with-lcd", action="store_true", help="Enable OLED LCD support.")
parser.add_argument("--with-ws2812", action="store_true", help="Enable WS2812 on PMOD1:0.")
target_group.add_argument("--with-spi-flash", action="store_true", help="Enable SPI Flash (MMAPed).")
target_group.add_argument("--with-lcd", action="store_true", help="Enable OLED LCD support.")
target_group.add_argument("--with-ws2812", action="store_true", help="Enable WS2812 on PMOD1:0.")
builder_args(parser)
soc_core_args(parser)

17
litex_boards/targets/logicbone.py
View file

@ -152,14 +152,15 @@ class BaseSoC(SoCCore):
def main():
from litex.soc.integration.soc import LiteXSoCArgumentParser
parser = LiteXSoCArgumentParser(description="LiteX SoC on Logicbone")
parser.add_argument("--build", action="store_true", help="Build bitstream.")
parser.add_argument("--load", action="store_true", help="Load bitstream.")
parser.add_argument("--toolchain", default="trellis", help="FPGA toolchain (trellis or diamond).")
parser.add_argument("--sys-clk-freq", default=75e6, help="System clock frequency.")
parser.add_argument("--device", default="45F", help="FPGA device (45F or 85F).")
parser.add_argument("--sdram-device", default="MT41K512M16", help="SDRAM device (MT41K512M16).")
parser.add_argument("--with-ethernet", action="store_true", help="Enable Ethernet support.")
parser.add_argument("--with-sdcard", action="store_true", help="Enable SDCard support.")
target_group = parser.add_argument_group(title="Target options")
target_group.add_argument("--build", action="store_true", help="Build bitstream.")
target_group.add_argument("--load", action="store_true", help="Load bitstream.")
target_group.add_argument("--toolchain", default="trellis", help="FPGA toolchain (trellis or diamond).")
target_group.add_argument("--sys-clk-freq", default=75e6, help="System clock frequency.")
target_group.add_argument("--device", default="45F", help="FPGA device (45F or 85F).")
target_group.add_argument("--sdram-device", default="MT41K512M16", help="SDRAM device (MT41K512M16).")
target_group.add_argument("--with-ethernet", action="store_true", help="Enable Ethernet support.")
target_group.add_argument("--with-sdcard", action="store_true", help="Enable SDCard support.")
builder_args(parser)
soc_core_args(parser)
trellis_args(parser)

11
litex_boards/targets/micronova_mercury2.py
View file

@ -137,11 +137,12 @@ class BaseSoC(SoCCore):
def main():
from litex.soc.integration.soc import LiteXSoCArgumentParser
parser = LiteXSoCArgumentParser(description="LiteX SoC on MicroNova Mercury2")
parser.add_argument("--toolchain", default="vivado", help="FPGA toolchain (vivado or symbiflow).")
parser.add_argument("--build", action="store_true", help="Build bitstream.")
parser.add_argument("--load", action="store_true", help="Load bitstream.")
parser.add_argument("--variant", default="a7-35", help="Board variant (a7-35 or a7-100).")
parser.add_argument("--sys-clk-freq", default=50e6, help="System clock frequency.")
target_group = parser.add_argument_group(title="Target options")
target_group.add_argument("--toolchain", default="vivado", help="FPGA toolchain (vivado or symbiflow).")
target_group.add_argument("--build", action="store_true", help="Build bitstream.")
target_group.add_argument("--load", action="store_true", help="Load bitstream.")
target_group.add_argument("--variant", default="a7-35", help="Board variant (a7-35 or a7-100).")
target_group.add_argument("--sys-clk-freq", default=50e6, help="System clock frequency.")
builder_args(parser)
soc_core_args(parser)

9
litex_boards/targets/mist.py
View file

@ -87,10 +87,11 @@ class BaseSoC(SoCCore):
def main():
from litex.soc.integration.soc import LiteXSoCArgumentParser
parser = LiteXSoCArgumentParser(description="LiteX SoC on MIST")
parser.add_argument("--build", action="store_true", help="Build bitstream.")
parser.add_argument("--load", action="store_true", help="Load bitstream.")
parser.add_argument("--sys-clk-freq", default=50e6, help="System clock frequency.")
parser.add_argument("--with-video-terminal", action="store_true", help="Enable Video Terminal (VGA).")
target_group = parser.add_argument_group(title="Target options")
target_group.add_argument("--build", action="store_true", help="Build bitstream.")
target_group.add_argument("--load", action="store_true", help="Load bitstream.")
target_group.add_argument("--sys-clk-freq", default=50e6, help="System clock frequency.")
target_group.add_argument("--with-video-terminal", action="store_true", help="Enable Video Terminal (VGA).")
builder_args(parser)
soc_core_args(parser)
args = parser.parse_args()

13
litex_boards/targets/mnt_rkx7.py
View file

@ -94,14 +94,15 @@ class BaseSoC(SoCCore):
def main():
from litex.soc.integration.soc import LiteXSoCArgumentParser
parser = LiteXSoCArgumentParser(description="LiteX SoC on MNT-RKX7")
parser.add_argument("--build", action="store_true", help="Build bitstream.")
parser.add_argument("--load", action="store_true", help="Load bitstream.")
parser.add_argument("--sys-clk-freq", default=100e6, help="System clock frequency.")
parser.add_argument("--with-spi-flash", action="store_true", help="Enable SPI Flash (MMAPed).")
sdopts = parser.add_mutually_exclusive_group()
target_group = parser.add_argument_group(title="Target options")
target_group.add_argument("--build", action="store_true", help="Build bitstream.")
target_group.add_argument("--load", action="store_true", help="Load bitstream.")
target_group.add_argument("--sys-clk-freq", default=100e6, help="System clock frequency.")
target_group.add_argument("--with-spi-flash", action="store_true", help="Enable SPI Flash (MMAPed).")
sdopts = target_group.add_mutually_exclusive_group()
sdopts.add_argument("--with-spi-sdcard", action="store_true", help="Enable SPI-mode SDCard support.")
sdopts.add_argument("--with-sdcard", action="store_true", help="Enable SDCard support.")
ethopts = parser.add_mutually_exclusive_group()
ethopts = target_group.add_mutually_exclusive_group()
ethopts.add_argument("--with-ethernet", action="store_true", help="Enable Ethernet support.")
ethopts.add_argument("--with-etherbone", action="store_true", help="Enable Etherbone support.")
builder_args(parser)

11
litex_boards/targets/muselab_icesugar.py
View file

@ -111,11 +111,12 @@ def flash(bios_flash_offset):
def main():
from litex.soc.integration.soc import LiteXSoCArgumentParser
parser = LiteXSoCArgumentParser(description="LiteX SoC on iCEBreaker")
parser.add_argument("--build", action="store_true", help="Build bitstream.")
parser.add_argument("--load", action="store_true", help="Load bitstream.")
parser.add_argument("--flash", action="store_true", help="Flash Bitstream.")
parser.add_argument("--sys-clk-freq", default=24e6, help="System clock frequency.")
parser.add_argument("--bios-flash-offset", default="0x40000", help="BIOS offset in SPI Flash.")
target_group = parser.add_argument_group(title="Target options")
target_group.add_argument("--build", action="store_true", help="Build bitstream.")
target_group.add_argument("--load", action="store_true", help="Load bitstream.")
target_group.add_argument("--flash", action="store_true", help="Flash Bitstream.")
target_group.add_argument("--sys-clk-freq", default=24e6, help="System clock frequency.")
target_group.add_argument("--bios-flash-offset", default="0x40000", help="BIOS offset in SPI Flash.")
builder_args(parser)
soc_core_args(parser)
args = parser.parse_args()

17
litex_boards/targets/muselab_icesugar_pro.py
View file

@ -132,16 +132,17 @@ class BaseSoC(SoCCore):
def main():
from litex.soc.integration.soc import LiteXSoCArgumentParser
parser = LiteXSoCArgumentParser(description="LiteX SoC on Colorlight i5")
parser.add_argument("--build", action="store_true", help="Build bitstream.")
parser.add_argument("--load", action="store_true", help="Load bitstream.")
parser.add_argument("--sys-clk-freq", default=60e6, help="System clock frequency.")
sdopts = parser.add_mutually_exclusive_group()
target_group = parser.add_argument_group(title="Target options")
target_group.add_argument("--build", action="store_true", help="Build bitstream.")
target_group.add_argument("--load", action="store_true", help="Load bitstream.")
target_group.add_argument("--sys-clk-freq", default=60e6, help="System clock frequency.")
sdopts = target_group.add_mutually_exclusive_group()
sdopts.add_argument("--with-spi-sdcard", action="store_true", help="Enable SPI-mode SDCard support.")
sdopts.add_argument("--with-sdcard", action="store_true", help="Enable SDCard support.")
parser.add_argument("--with-spi-flash", action="store_true", help="Enable SPI Flash (MMAPed).")
parser.add_argument("--use-internal-osc", action="store_true", help="Use internal oscillator.")
parser.add_argument("--sdram-rate", default="1:1", help="SDRAM Rate (1:1 Full Rate or 1:2 Half Rate).")
viopts = parser.add_mutually_exclusive_group()
target_group.add_argument("--with-spi-flash", action="store_true", help="Enable SPI Flash (MMAPed).")
target_group.add_argument("--use-internal-osc", action="store_true", help="Use internal oscillator.")
target_group.add_argument("--sdram-rate", default="1:1", help="SDRAM Rate (1:1 Full Rate or 1:2 Half Rate).")
viopts = target_group.add_mutually_exclusive_group()
viopts.add_argument("--with-video-terminal", action="store_true", help="Enable Video Terminal (HDMI).")
viopts.add_argument("--with-video-framebuffer", action="store_true", help="Enable Video Framebuffer (HDMI).")
builder_args(parser)

9
litex_boards/targets/myminieye_runber.py
View file

@ -59,10 +59,11 @@ class BaseSoC(SoCCore):
def main():
from litex.soc.integration.soc import LiteXSoCArgumentParser
parser = LiteXSoCArgumentParser(description="LiteX SoC on Runber")
parser.add_argument("--build", action="store_true", help="Build bitstream.")
parser.add_argument("--load", action="store_true", help="Load bitstream.")
parser.add_argument("--flash", action="store_true", help="Flash Bitstream.")
parser.add_argument("--sys-clk-freq",default=12e6, help="System clock frequency.")
target_group = parser.add_argument_group(title="Target options")
target_group.add_argument("--build", action="store_true", help="Build bitstream.")
target_group.add_argument("--load", action="store_true", help="Load bitstream.")
target_group.add_argument("--flash", action="store_true", help="Flash Bitstream.")
target_group.add_argument("--sys-clk-freq",default=12e6, help="System clock frequency.")
builder_args(parser)
soc_core_args(parser)
args = parser.parse_args()

11
litex_boards/targets/numato_aller.py
View file

@ -98,11 +98,12 @@ class BaseSoC(SoCCore):
def main():
from litex.soc.integration.soc import LiteXSoCArgumentParser
parser = LiteXSoCArgumentParser(description="LiteX SoC on Aller")
parser.add_argument("--build", action="store_true", help="Build bitstream.")
parser.add_argument("--load", action="store_true", help="Load bitstream.")
parser.add_argument("--sys-clk-freq", default=100e6, help="System clock frequency.")
parser.add_argument("--with-pcie", action="store_true", help="Enable PCIe support.")
parser.add_argument("--driver", action="store_true", help="Generate LitePCIe driver.")
target_group = parser.add_argument_group(title="Target options")
target_group.add_argument("--build", action="store_true", help="Build bitstream.")
target_group.add_argument("--load", action="store_true", help="Load bitstream.")
target_group.add_argument("--sys-clk-freq", default=100e6, help="System clock frequency.")
target_group.add_argument("--with-pcie", action="store_true", help="Enable PCIe support.")
target_group.add_argument("--driver", action="store_true", help="Generate LitePCIe driver.")
builder_args(parser)
soc_core_args(parser)
args = parser.parse_args()

9
litex_boards/targets/numato_mimas_a7.py
View file

@ -90,10 +90,11 @@ class BaseSoC(SoCCore):
def main():
from litex.soc.integration.soc import LiteXSoCArgumentParser
parser = LiteXSoCArgumentParser(description="LiteX SoC on Mimas A7")
parser.add_argument("--build", action="store_true", help="Build bitstream.")
parser.add_argument("--load", action="store_true", help="Load bitstream.")
parser.add_argument("--sys-clk-freq", default=100e6, help="System clock frequency.")
parser.add_argument("--with-ethernet", action="store_true", help="Enable Ethernet support.")
target_group = parser.add_argument_group(title="Target options")
target_group.add_argument("--build", action="store_true", help="Build bitstream.")
target_group.add_argument("--load", action="store_true", help="Load bitstream.")
target_group.add_argument("--sys-clk-freq", default=100e6, help="System clock frequency.")
target_group.add_argument("--with-ethernet", action="store_true", help="Enable Ethernet support.")
builder_args(parser)
soc_core_args(parser)
vivado_build_args(parser)

11
litex_boards/targets/numato_nereid.py
View file

@ -88,11 +88,12 @@ class BaseSoC(SoCCore):
def main():
from litex.soc.integration.soc import LiteXSoCArgumentParser
parser = LiteXSoCArgumentParser(description="LiteX SoC on Nereid")
parser.add_argument("--build", action="store_true", help="Build bitstream.")
parser.add_argument("--load", action="store_true", help="Load bitstream.")
parser.add_argument("--sys-clk-freq", default=100e6, help="System clock frequency.")
parser.add_argument("--with-pcie", action="store_true", help="Enable PCIe support.")
parser.add_argument("--driver", action="store_true", help="Generate PCIe driver.")
target_group = parser.add_argument_group(title="Target options")
target_group.add_argument("--build", action="store_true", help="Build bitstream.")
target_group.add_argument("--load", action="store_true", help="Load bitstream.")
target_group.add_argument("--sys-clk-freq", default=100e6, help="System clock frequency.")
target_group.add_argument("--with-pcie", action="store_true", help="Enable PCIe support.")
target_group.add_argument("--driver", action="store_true", help="Generate PCIe driver.")
builder_args(parser)
soc_core_args(parser)
args = parser.parse_args()

11
litex_boards/targets/numato_tagus.py
View file

@ -98,11 +98,12 @@ class BaseSoC(SoCCore):
def main():
from litex.soc.integration.soc import LiteXSoCArgumentParser
parser = LiteXSoCArgumentParser(description="LiteX SoC on Tagus")
parser.add_argument("--build", action="store_true", help="Build bitstream.")
parser.add_argument("--load", action="store_true", help="Load bitstream.")
parser.add_argument("--sys-clk-freq", default=100e6, help="System clock frequency.")
parser.add_argument("--with-pcie", action="store_true", help="Enable PCIe support.")
parser.add_argument("--driver", action="store_true", help="Generate PCIe driver.")
target_group = parser.add_argument_group(title="Target options")
target_group.add_argument("--build", action="store_true", help="Build bitstream.")
target_group.add_argument("--load", action="store_true", help="Load bitstream.")
target_group.add_argument("--sys-clk-freq", default=100e6, help="System clock frequency.")
target_group.add_argument("--with-pcie", action="store_true", help="Enable PCIe support.")
target_group.add_argument("--driver", action="store_true", help="Generate PCIe driver.")
builder_args(parser)
soc_core_args(parser)
args = parser.parse_args()

13
litex_boards/targets/pano_logic_g2.py
View file

@ -80,14 +80,15 @@ class BaseSoC(SoCCore):
def main():
from litex.soc.integration.soc import LiteXSoCArgumentParser
parser = LiteXSoCArgumentParser(description="LiteX SoC on Pano Logic G2")
parser.add_argument("--build", action="store_true", help="Build bitstream.")
parser.add_argument("--load", action="store_true", help="Load bitstream.")
parser.add_argument("--revision", default="c", help="Board revision (b or c).")
parser.add_argument("--sys-clk-freq", default=50e6, help="System clock frequency.")
ethopts = parser.add_mutually_exclusive_group()
target_group = parser.add_argument_group(title="Target options")
target_group.add_argument("--build", action="store_true", help="Build bitstream.")
target_group.add_argument("--load", action="store_true", help="Load bitstream.")
target_group.add_argument("--revision", default="c", help="Board revision (b or c).")
target_group.add_argument("--sys-clk-freq", default=50e6, help="System clock frequency.")
ethopts = target_group.add_mutually_exclusive_group()
ethopts.add_argument("--with-ethernet", action="store_true", help="Enable Ethernet support.")
ethopts.add_argument("--with-etherbone", action="store_true", help="Enable Etherbone support.")
parser.add_argument("--eth-ip", default="192.168.1.50", type=str, help="Ethernet/Etherbone IP address.")
target_group.add_argument("--eth-ip", default="192.168.1.50", type=str, help="Ethernet/Etherbone IP address.")
builder_args(parser)
soc_core_args(parser)
args = parser.parse_args()

15
litex_boards/targets/qmtech_10cl006.py
View file

@ -103,15 +103,16 @@ class BaseSoC(SoCCore):
def main():
from litex.soc.integration.soc import LiteXSoCArgumentParser
parser = LiteXSoCArgumentParser(description="LiteX SoC on QMTECH 10CL006")
parser.add_argument("--build", action="store_true", help="Build bitstream.")
parser.add_argument("--load", action="store_true", help="Load bitstream.")
parser.add_argument("--sys-clk-freq", default=50e6, help="System clock frequency.")
parser.add_argument("--sdram-rate", default="1:2", help="SDRAM Rate (1:1 Full Rate or 1:2 Half Rate).")
parser.add_argument("--with-daughterboard", action="store_true", help="Board plugged into the QMTech daughterboard.")
sdopts = parser.add_mutually_exclusive_group()
target_group = parser.add_argument_group(title="Target options")
target_group.add_argument("--build", action="store_true", help="Build bitstream.")
target_group.add_argument("--load", action="store_true", help="Load bitstream.")
target_group.add_argument("--sys-clk-freq", default=50e6, help="System clock frequency.")
target_group.add_argument("--sdram-rate", default="1:2", help="SDRAM Rate (1:1 Full Rate or 1:2 Half Rate).")
target_group.add_argument("--with-daughterboard", action="store_true", help="Board plugged into the QMTech daughterboard.")
sdopts = target_group.add_mutually_exclusive_group()
sdopts.add_argument("--with-spi-sdcard", action="store_true", help="Enable SPI-mode SDCard support.")
sdopts.add_argument("--with-sdcard", action="store_true", help="Enable SDCard support.")
parser.add_argument("--with-spi-flash", action="store_true", help="Enable SPI Flash (MMAPed).")
target_group.add_argument("--with-spi-flash", action="store_true", help="Enable SPI Flash (MMAPed).")
builder_args(parser)
soc_core_args(parser)
args = parser.parse_args()

23
litex_boards/targets/qmtech_5cefa2.py
View file

@ -130,21 +130,22 @@ class BaseSoC(SoCCore):
def main():
from litex.soc.integration.soc import LiteXSoCArgumentParser
parser = LiteXSoCArgumentParser(description="LiteX SoC on QMTECH 5CEFA2")
parser.add_argument("--build", action="store_true", help="Build bitstream.")
parser.add_argument("--load", action="store_true", help="Load bitstream.")
parser.add_argument("--sys-clk-freq", default=105e6, help="System clock frequency.")
parser.add_argument("--sdram-rate", default="1:1", help="SDRAM Rate (1:1 Full Rate or 1:2 Half Rate).")
parser.add_argument("--with-daughterboard", action="store_true", help="Board plugged into the QMTech daughterboard.")
ethopts = parser.add_mutually_exclusive_group()
target_group = parser.add_argument_group(title="Target options")
target_group.add_argument("--build", action="store_true", help="Build bitstream.")
target_group.add_argument("--load", action="store_true", help="Load bitstream.")
target_group.add_argument("--sys-clk-freq", default=105e6, help="System clock frequency.")
target_group.add_argument("--sdram-rate", default="1:1", help="SDRAM Rate (1:1 Full Rate or 1:2 Half Rate).")
target_group.add_argument("--with-daughterboard", action="store_true", help="Board plugged into the QMTech daughterboard.")
ethopts = target_group.add_mutually_exclusive_group()
ethopts.add_argument("--with-ethernet", action="store_true", help="Enable Ethernet support.")
ethopts.add_argument("--with-etherbone", action="store_true", help="Enable Etherbone support")
parser.add_argument("--eth-ip", default="192.168.1.50", type=str, help="Ethernet/Etherbone IP address.")
parser.add_argument("--eth-dynamic-ip", action="store_true", help="Enable dynamic Ethernet IP addresses setting.")
sdopts = parser.add_mutually_exclusive_group()
target_group.add_argument("--eth-ip", default="192.168.1.50", type=str, help="Ethernet/Etherbone IP address.")
target_group.add_argument("--eth-dynamic-ip", action="store_true", help="Enable dynamic Ethernet IP addresses setting.")
sdopts = target_group.add_mutually_exclusive_group()
sdopts.add_argument("--with-spi-sdcard", action="store_true", help="Enable SPI-mode SDCard support.")
sdopts.add_argument("--with-sdcard", action="store_true", help="Enable SDCard support.")
parser.add_argument("--with-spi-flash", action="store_true", help="Enable SPI Flash (MMAPed).")
viopts = parser.add_mutually_exclusive_group()
target_group.add_argument("--with-spi-flash", action="store_true", help="Enable SPI Flash (MMAPed).")
viopts = target_group.add_mutually_exclusive_group()
viopts.add_argument("--with-video-terminal", action="store_true", help="Enable Video Terminal (VGA).")
viopts.add_argument("--with-video-framebuffer", action="store_true", help="Enable Video Framebuffer (VGA).")
builder_args(parser)

23
litex_boards/targets/qmtech_ep4cex5.py
View file

@ -126,21 +126,22 @@ class BaseSoC(SoCCore):
def main():
from litex.soc.integration.soc import LiteXSoCArgumentParser
parser = LiteXSoCArgumentParser(description="LiteX SoC on QMTECH EP4CE15")
parser.add_argument("--build", action="store_true", help="Build bitstream.")
parser.add_argument("--load", action="store_true", help="Load bitstream.")
parser.add_argument("--variant", default="ep4ce15", help="Board variant (ep4ce15 or ep4ce55).")
parser.add_argument("--sys-clk-freq", default=50e6, help="System clock frequency.")
parser.add_argument("--sdram-rate", default="1:1", help="SDRAM Rate (1:1 Full Rate or 1:2 Half Rate).")
parser.add_argument("--with-daughterboard", action="store_true", help="Board plugged into the QMTech daughterboard.")
ethopts = parser.add_mutually_exclusive_group()
target_group = parser.add_argument_group(title="Target options")
target_group.add_argument("--build", action="store_true", help="Build bitstream.")
target_group.add_argument("--load", action="store_true", help="Load bitstream.")
target_group.add_argument("--variant", default="ep4ce15", help="Board variant (ep4ce15 or ep4ce55).")
target_group.add_argument("--sys-clk-freq", default=50e6, help="System clock frequency.")
target_group.add_argument("--sdram-rate", default="1:1", help="SDRAM Rate (1:1 Full Rate or 1:2 Half Rate).")
target_group.add_argument("--with-daughterboard", action="store_true", help="Board plugged into the QMTech daughterboard.")
ethopts = target_group.add_mutually_exclusive_group()
ethopts.add_argument("--with-ethernet", action="store_true", help="Enable Ethernet support.")
ethopts.add_argument("--with-etherbone", action="store_true", help="Enable Etherbone support.")
parser.add_argument("--eth-ip", default="192.168.1.50", type=str, help="Ethernet/Etherbone IP address.")
parser.add_argument("--eth-dynamic-ip", action="store_true", help="Enable dynamic Ethernet IP addresses setting.")
sdopts = parser.add_mutually_exclusive_group()
target_group.add_argument("--eth-ip", default="192.168.1.50", type=str, help="Ethernet/Etherbone IP address.")
target_group.add_argument("--eth-dynamic-ip", action="store_true", help="Enable dynamic Ethernet IP addresses setting.")
sdopts = target_group.add_mutually_exclusive_group()
sdopts.add_argument("--with-spi-sdcard", action="store_true", help="Enable SPI-mode SDCard support.")
sdopts.add_argument("--with-sdcard", action="store_true", help="Enable SDCard support.")
viopts = parser.add_mutually_exclusive_group()
viopts = target_group.add_mutually_exclusive_group()
viopts.add_argument("--with-video-terminal", action="store_true", help="Enable Video Terminal (VGA).")
viopts.add_argument("--with-video-framebuffer", action="store_true", help="Enable Video Framebuffer (VGA).")

19
litex_boards/targets/qmtech_wukong.py
View file

@ -128,19 +128,20 @@ class BaseSoC(SoCCore):
def main():
from litex.soc.integration.soc import LiteXSoCArgumentParser
parser = LiteXSoCArgumentParser(description="LiteX SoC on QMTECH Wukong Board")
parser.add_argument("--build", action="store_true", help="Build bitstream.")
parser.add_argument("--load", action="store_true", help="Load bitstream.")
parser.add_argument("--sys-clk-freq", default=100e6, help="System clock frequency.")
parser.add_argument("--board-version", default=1, help="Board version (1 or 2).")
parser.add_argument("--speed-grade", default=-1, help="FPGA speed grade (-1 or -2).")
ethopts = parser.add_mutually_exclusive_group()
target_group = parser.add_argument_group(title="Target options")
target_group.add_argument("--build", action="store_true", help="Build bitstream.")
target_group.add_argument("--load", action="store_true", help="Load bitstream.")
target_group.add_argument("--sys-clk-freq", default=100e6, help="System clock frequency.")
target_group.add_argument("--board-version", default=1, help="Board version (1 or 2).")
target_group.add_argument("--speed-grade", default=-1, help="FPGA speed grade (-1 or -2).")
ethopts = target_group.add_mutually_exclusive_group()
ethopts.add_argument("--with-ethernet", action="store_true", help="Enable Ethernet support.")
ethopts.add_argument("--with-etherbone", action="store_true", help="Enable Etherbone support.")
parser.add_argument("--eth-ip", default="192.168.1.50", type=str, help="Ethernet/Etherbone IP address.")
sdopts = parser.add_mutually_exclusive_group()
target_group.add_argument("--eth-ip", default="192.168.1.50", type=str, help="Ethernet/Etherbone IP address.")
sdopts = target_group.add_mutually_exclusive_group()
sdopts.add_argument("--with-spi-sdcard", action="store_true", help="Enable SPI-mode SDCard support.")
sdopts.add_argument("--with-sdcard", action="store_true", help="Enable SDCard support.")
viopts = parser.add_mutually_exclusive_group()
viopts = target_group.add_mutually_exclusive_group()
viopts.add_argument("--with-video-terminal", action="store_true", help="Enable Video Terminal (HDMI).")
viopts.add_argument("--with-video-framebuffer", action="store_true", help="Enable Video Framebuffer (HDMI).")
builder_args(parser)

25
litex_boards/targets/qmtech_xc7a35t.py
View file

@ -139,22 +139,23 @@ class BaseSoC(SoCCore):
def main():
from litex.soc.integration.soc import LiteXSoCArgumentParser
parser = LiteXSoCArgumentParser(description="LiteX SoC on QMTech XC7A35T")
parser.add_argument("--toolchain", default="vivado", help="FPGA toolchain (vivado or symbiflow).")
parser.add_argument("--build", action="store_true", help="Build bitstream.")
parser.add_argument("--load", action="store_true", help="Load bitstream.")
parser.add_argument("--sys-clk-freq", default=100e6, help="System clock frequency.")
parser.add_argument("--with-daughterboard", action="store_true", help="Board plugged into the QMTech daughterboard.")
ethopts = parser.add_mutually_exclusive_group()
target_group = parser.add_argument_group(title="Target options")
target_group.add_argument("--toolchain", default="vivado", help="FPGA toolchain (vivado or symbiflow).")
target_group.add_argument("--build", action="store_true", help="Build bitstream.")
target_group.add_argument("--load", action="store_true", help="Load bitstream.")
target_group.add_argument("--sys-clk-freq", default=100e6, help="System clock frequency.")
target_group.add_argument("--with-daughterboard", action="store_true", help="Board plugged into the QMTech daughterboard.")
ethopts = target_group.add_mutually_exclusive_group()
ethopts.add_argument("--with-ethernet", action="store_true", help="Enable Ethernet support.")
ethopts.add_argument("--with-etherbone", action="store_true", help="Enable Etherbone support.")
parser.add_argument("--eth-ip", default="192.168.1.50", type=str, help="Ethernet/Etherbone IP address.")
parser.add_argument("--eth-dynamic-ip", action="store_true", help="Enable dynamic Ethernet IP addresses setting.")
sdopts = parser.add_mutually_exclusive_group()
target_group.add_argument("--eth-ip", default="192.168.1.50", type=str, help="Ethernet/Etherbone IP address.")
target_group.add_argument("--eth-dynamic-ip", action="store_true", help="Enable dynamic Ethernet IP addresses setting.")
sdopts = target_group.add_mutually_exclusive_group()
sdopts.add_argument("--with-spi-sdcard", action="store_true", help="Enable SPI-mode SDCard support.")
sdopts.add_argument("--with-sdcard", action="store_true", help="Enable SDCard support.")
parser.add_argument("--with-jtagbone", action="store_true", help="Enable Jtagbone support.")
parser.add_argument("--with-spi-flash", action="store_true", help="Enable SPI Flash (MMAPed).")
viopts = parser.add_mutually_exclusive_group()
target_group.add_argument("--with-jtagbone", action="store_true", help="Enable Jtagbone support.")
target_group.add_argument("--with-spi-flash", action="store_true", help="Enable SPI Flash (MMAPed).")
viopts = target_group.add_mutually_exclusive_group()
viopts.add_argument("--with-video-terminal", action="store_true", help="Enable Video Terminal (VGA).")
viopts.add_argument("--with-video-framebuffer", action="store_true", help="Enable Video Framebuffer (VGA).")
builder_args(parser)

3
litex_boards/targets/quicklogic_quickfeather.py
View file

@ -91,7 +91,8 @@ class BaseSoC(SoCCore):
def main():
from litex.soc.integration.soc import LiteXSoCArgumentParser
parser = LiteXSoCArgumentParser(description="LiteX SoC on QuickLogic QuickFeather")
parser.add_argument("--build", action="store_true", help="Build bitstream.")
target_group = parser.add_argument_group(title="Target options")
target_group.add_argument("--build", action="store_true", help="Build bitstream.")
soc_core_args(parser)
parser.set_defaults(cpu_type="eos_s3")
args = parser.parse_args()

7
litex_boards/targets/qwertyembedded_beaglewire.py
View file

@ -110,9 +110,10 @@ class BaseSoC(SoCCore):
def main():
from litex.soc.integration.soc import LiteXSoCArgumentParser
parser = LiteXSoCArgumentParser(description="LiteX SoC on Beaglewire")
parser.add_argument("--build", action="store_true", help="Build bitstream.")
parser.add_argument("--bios-flash-offset", default="0x60000", help="BIOS offset in SPI Flash.")
parser.add_argument("--sys-clk-freq", default=50e6, help="System clock frequency.")
target_group = parser.add_argument_group(title="Target options")
target_group.add_argument("--build", action="store_true", help="Build bitstream.")
target_group.add_argument("--bios-flash-offset", default="0x60000", help="BIOS offset in SPI Flash.")
target_group.add_argument("--sys-clk-freq", default=50e6, help="System clock frequency.")
builder_args(parser)
soc_core_args(parser)
args = parser.parse_args()

25
litex_boards/targets/radiona_ulx3s.py
View file

@ -146,20 +146,21 @@ class BaseSoC(SoCCore):
def main():
from litex.soc.integration.soc import LiteXSoCArgumentParser
parser = LiteXSoCArgumentParser(description="LiteX SoC on ULX3S")
parser.add_argument("--build", action="store_true", help="Build bitstream.")
parser.add_argument("--load", action="store_true", help="Load bitstream.")
parser.add_argument("--toolchain", default="trellis", help="FPGA toolchain (trellis or diamond).")
parser.add_argument("--device", default="LFE5U-45F", help="FPGA device (LFE5U-12F, LFE5U-25F, LFE5U-45F or LFE5U-85F).")
parser.add_argument("--revision", default="2.0", help="Board revision (2.0 or 1.7).")
parser.add_argument("--sys-clk-freq", default=50e6, help="System clock frequency.")
parser.add_argument("--sdram-module", default="MT48LC16M16", help="SDRAM module (MT48LC16M16, AS4C32M16 or AS4C16M16).")
parser.add_argument("--with-spi-flash", action="store_true", help="Enable SPI Flash (MMAPed).")
sdopts = parser.add_mutually_exclusive_group()
target_group = parser.add_argument_group(title="Target options")
target_group.add_argument("--build", action="store_true", help="Build bitstream.")
target_group.add_argument("--load", action="store_true", help="Load bitstream.")
target_group.add_argument("--toolchain", default="trellis", help="FPGA toolchain (trellis or diamond).")
target_group.add_argument("--device", default="LFE5U-45F", help="FPGA device (LFE5U-12F, LFE5U-25F, LFE5U-45F or LFE5U-85F).")
target_group.add_argument("--revision", default="2.0", help="Board revision (2.0 or 1.7).")
target_group.add_argument("--sys-clk-freq", default=50e6, help="System clock frequency.")
target_group.add_argument("--sdram-module", default="MT48LC16M16", help="SDRAM module (MT48LC16M16, AS4C32M16 or AS4C16M16).")
target_group.add_argument("--with-spi-flash", action="store_true", help="Enable SPI Flash (MMAPed).")
sdopts = target_group.add_mutually_exclusive_group()
sdopts.add_argument("--with-spi-sdcard", action="store_true", help="Enable SPI-mode SDCard support.")
sdopts.add_argument("--with-sdcard", action="store_true", help="Enable SDCard support.")
parser.add_argument("--with-oled", action="store_true", help="Enable SDD1331 OLED support.")
parser.add_argument("--sdram-rate", default="1:1", help="SDRAM Rate (1:1 Full Rate or 1:2 Half Rate).")
viopts = parser.add_mutually_exclusive_group()
target_group.add_argument("--with-oled", action="store_true", help="Enable SDD1331 OLED support.")
target_group.add_argument("--sdram-rate", default="1:1", help="SDRAM Rate (1:1 Full Rate or 1:2 Half Rate).")
viopts = target_group.add_mutually_exclusive_group()
viopts.add_argument("--with-video-terminal", action="store_true", help="Enable Video Terminal (HDMI).")
viopts.add_argument("--with-video-framebuffer", action="store_true", help="Enable Video Framebuffer (HDMI).")
builder_args(parser)

13
litex_boards/targets/rcs_arctic_tern_bmc_card.py
View file

@ -166,14 +166,15 @@ class BaseSoC(SoCCore):
def main():
from litex.soc.integration.soc import LiteXSoCArgumentParser
parser = LiteXSoCArgumentParser(description="LiteX SoC on Arctic Tern (BMC card carrier)")
parser.add_argument("--build", action="store_true", help="Build bitstream")
parser.add_argument("--load", action="store_true", help="Load bitstream")
parser.add_argument("--toolchain", default="trellis", help="FPGA toolchain: trellis (default) or diamond")
parser.add_argument("--sys-clk-freq", default=60e6, help="System clock frequency (default: 60MHz)")
ethopts = parser.add_mutually_exclusive_group()
target_group = parser.add_argument_group(title="Target options")
target_group.add_argument("--build", action="store_true", help="Build bitstream")
target_group.add_argument("--load", action="store_true", help="Load bitstream")
target_group.add_argument("--toolchain", default="trellis", help="FPGA toolchain: trellis (default) or diamond")
target_group.add_argument("--sys-clk-freq", default=60e6, help="System clock frequency (default: 60MHz)")
ethopts = target_group.add_mutually_exclusive_group()
ethopts.add_argument("--with-ethernet", action="store_true", help="Enable Ethernet support.")
ethopts.add_argument("--with-etherbone", action="store_true", help="Enable Etherbone support.")
parser.add_argument("--eth-ip", default="192.168.1.50", type=str, help="Ethernet/Etherbone IP address.")
target_group.add_argument("--eth-ip", default="192.168.1.50", type=str, help="Ethernet/Etherbone IP address.")
builder_args(parser)
soc_core_args(parser)
trellis_args(parser)

9
litex_boards/targets/redpitaya.py
View file

@ -92,10 +92,11 @@ class BaseSoC(SoCCore):
def main():
from litex.soc.integration.soc import LiteXSoCArgumentParser
parser = LiteXSoCArgumentParser(description="LiteX SoC on Zedboard")
parser.add_argument("--build", action="store_true", help="Build bitstream.")
parser.add_argument("--load", action="store_true", help="Load bitstream.")
parser.add_argument("--sys-clk-freq", default=100e6, help="System clock frequency.")
parser.add_argument("--board", default="redpitaya14", help="Board type (redpitaya14 or redpitaya16).")
target_group = parser.add_argument_group(title="Target options")
target_group.add_argument("--build", action="store_true", help="Build bitstream.")
target_group.add_argument("--load", action="store_true", help="Load bitstream.")
target_group.add_argument("--sys-clk-freq", default=100e6, help="System clock frequency.")
target_group.add_argument("--board", default="redpitaya14", help="Board type (redpitaya14 or redpitaya16).")
builder_args(parser)
soc_core_args(parser)
vivado_build_args(parser)

9
litex_boards/targets/rz_easyfpga.py
View file

@ -95,10 +95,11 @@ class BaseSoC(SoCCore):
def main():
from litex.soc.integration.soc import LiteXSoCArgumentParser
parser = LiteXSoCArgumentParser(description="LiteX SoC on RZ-EasyFPGA")
parser.add_argument("--build", action="store_true", help="Build bitstream.")
parser.add_argument("--load", action="store_true", help="Load bitstream.")
parser.add_argument("--sys-clk-freq", default=50e6, help="System clock frequency.")
parser.add_argument("--sdram-rate", default="1:1", help="SDRAM Rate (1:1 Full Rate or 1:2 Half Rate).")
target_group = parser.add_argument_group(title="Target options")
target_group.add_argument("--build", action="store_true", help="Build bitstream.")
target_group.add_argument("--load", action="store_true", help="Load bitstream.")
target_group.add_argument("--sys-clk-freq", default=50e6, help="System clock frequency.")
target_group.add_argument("--sdram-rate", default="1:1", help="SDRAM Rate (1:1 Full Rate or 1:2 Half Rate).")
builder_args(parser)
soc_core_args(parser)
args = parser.parse_args()

5
litex_boards/targets/saanlima_pipistrello.py
View file

@ -191,8 +191,9 @@ class BaseSoC(SoCCore):
def main():
from litex.soc.integration.soc import LiteXSoCArgumentParser
parser = LiteXSoCArgumentParser(description="LiteX SoC on Pipistrello")
parser.add_argument("--build", action="store_true", help="Build bitstream.")
parser.add_argument("--load", action="store_true", help="Load bitstream.")
target_group = parser.add_argument_group(title="Target options")
target_group.add_argument("--build", action="store_true", help="Build bitstream.")
target_group.add_argument("--load", action="store_true", help="Load bitstream.")
builder_args(parser)
soc_core_args(parser)
args = parser.parse_args()

11
litex_boards/targets/scarabhardware_minispartan6.py
View file

@ -105,11 +105,12 @@ class BaseSoC(SoCCore):
def main():
from litex.soc.integration.soc import LiteXSoCArgumentParser
parser = LiteXSoCArgumentParser(description="LiteX SoC on MiniSpartan6")
parser.add_argument("--build", action="store_true", help="Build bitstream.")
parser.add_argument("--load", action="store_true", help="Load bitstream.")
parser.add_argument("--sys-clk-freq", default=80e6, help="System clock frequency.")
parser.add_argument("--sdram-rate", default="1:1", help="SDRAM Rate (1:1 Full Rate or 1:2 Half Rate).")
viopts = parser.add_mutually_exclusive_group()
target_group = parser.add_argument_group(title="Target options")
target_group.add_argument("--build", action="store_true", help="Build bitstream.")
target_group.add_argument("--load", action="store_true", help="Load bitstream.")
target_group.add_argument("--sys-clk-freq", default=80e6, help="System clock frequency.")
target_group.add_argument("--sdram-rate", default="1:1", help="SDRAM Rate (1:1 Full Rate or 1:2 Half Rate).")
viopts = target_group.add_mutually_exclusive_group()
viopts.add_argument("--with-video-terminal", action="store_true", help="Enable Video Terminal (HDMI).")
viopts.add_argument("--with-video-framebuffer", action="store_true", help="Enable Video Framebuffer (HDMI).")
builder_args(parser)

11
litex_boards/targets/seeedstudio_spartan_edge_accelerator.py
View file

@ -108,11 +108,12 @@ class BaseSoC(SoCCore):
def main():
from litex.soc.integration.soc import LiteXSoCArgumentParser
parser = LiteXSoCArgumentParser(description="LiteX SoC on Spartan Edge Accelerator")
parser.add_argument("--build", action="store_true", help="Build bitstream.")
parser.add_argument("--sys-clk-freq", default=100e6, help="System clock frequency.")
parser.add_argument("--with-jtagbone", action="store_true", help="Enable Jtagbone support.")
parser.add_argument("--with-video-terminal", action="store_true", help="Enable Video Colorbars (HDMI).")
parser.add_argument("--with-neopixel", action="store_true", help="Enable onboard 2 Neopixels Leds.")
target_group = parser.add_argument_group(title="Target options")
target_group.add_argument("--build", action="store_true", help="Build bitstream.")
target_group.add_argument("--sys-clk-freq", default=100e6, help="System clock frequency.")
target_group.add_argument("--with-jtagbone", action="store_true", help="Enable Jtagbone support.")
target_group.add_argument("--with-video-terminal", action="store_true", help="Enable Video Colorbars (HDMI).")
target_group.add_argument("--with-neopixel", action="store_true", help="Enable onboard 2 Neopixels Leds.")
builder_args(parser)
soc_core_args(parser)

13
litex_boards/targets/siglent_sds1104xe.py
View file

@ -164,12 +164,13 @@ class BaseSoC(SoCCore):
def main():
from litex.soc.integration.soc import LiteXSoCArgumentParser
parser = LiteXSoCArgumentParser(description="LiteX SoC on SDS1104X-E")
parser.add_argument("--build", action="store_true", help="Build bitstream.")
parser.add_argument("--load", action="store_true", help="Load bitstream.")
parser.add_argument("--sys-clk-freq", default=100e6, help="System clock frequency.")
parser.add_argument("--with-etherbone", action="store_true", help="Enable Etherbone support.")
parser.add_argument("--eth-ip", default="192.168.1.50", type=str, help="Ethernet/Etherbone IP address.")
viopts = parser.add_mutually_exclusive_group()
target_group = parser.add_argument_group(title="Target options")
target_group.add_argument("--build", action="store_true", help="Build bitstream.")
target_group.add_argument("--load", action="store_true", help="Load bitstream.")
target_group.add_argument("--sys-clk-freq", default=100e6, help="System clock frequency.")
target_group.add_argument("--with-etherbone", action="store_true", help="Enable Etherbone support.")
target_group.add_argument("--eth-ip", default="192.168.1.50", type=str, help="Ethernet/Etherbone IP address.")
viopts = target_group.add_mutually_exclusive_group()
viopts.add_argument("--with-video-terminal", action="store_true", help="Enable Video Terminal (HDMI).")
viopts.add_argument("--with-video-framebuffer", action="store_true", help="Enable Video Framebuffer (HDMI).")
builder_args(parser)

9
litex_boards/targets/simple.py
View file

@ -46,10 +46,11 @@ class BaseSoC(SoCCore):
def main():
from litex.soc.integration.soc import LiteXSoCArgumentParser
parser = LiteXSoCArgumentParser(description="Generic LiteX SoC")
parser.add_argument("platform", help="Module name of the platform to build for.")
parser.add_argument("--build", action="store_true", help="Build bitstream.")
parser.add_argument("--load", action="store_true", help="Load bitstream.")
parser.add_argument("--toolchain", default=None, help="FPGA toolchain.")
target_group = parser.add_argument_group(title="Target options")
target_group.add_argument("platform", help="Module name of the platform to build for.")
target_group.add_argument("--build", action="store_true", help="Build bitstream.")
target_group.add_argument("--load", action="store_true", help="Load bitstream.")
target_group.add_argument("--toolchain", default=None, help="FPGA toolchain.")
builder_args(parser)
soc_core_args(parser)
args = parser.parse_args()

9
litex_boards/targets/sipeed_tang_nano.py
View file

@ -85,10 +85,11 @@ class BaseSoC(SoCMini):
def main():
from litex.soc.integration.soc import LiteXSoCArgumentParser
parser = LiteXSoCArgumentParser(description="LiteX SoC on Tang Nano")
parser.add_argument("--build", action="store_true", help="Build bitstream.")
parser.add_argument("--load", action="store_true", help="Load bitstream.")
parser.add_argument("--flash", action="store_true", help="Flash Bitstream.")
parser.add_argument("--sys-clk-freq",default=48e6, help="System clock frequency.")
target_group = parser.add_argument_group(title="Target options")
target_group.add_argument("--build", action="store_true", help="Build bitstream.")
target_group.add_argument("--load", action="store_true", help="Load bitstream.")
target_group.add_argument("--flash", action="store_true", help="Flash Bitstream.")
target_group.add_argument("--sys-clk-freq",default=48e6, help="System clock frequency.")
builder_args(parser)
soc_core_args(parser)
args = parser.parse_args()

9
litex_boards/targets/sipeed_tang_nano_4k.py
View file

@ -140,10 +140,11 @@ class BaseSoC(SoCCore):
def main():
from litex.soc.integration.soc import LiteXSoCArgumentParser
parser = LiteXSoCArgumentParser(description="LiteX SoC on Tang Nano 4K")
parser.add_argument("--build", action="store_true", help="Build bitstream.")
parser.add_argument("--load", action="store_true", help="Load bitstream.")
parser.add_argument("--flash", action="store_true", help="Flash Bitstream.")
parser.add_argument("--sys-clk-freq",default=27e6, help="System clock frequency.")
target_group = parser.add_argument_group(title="Target options")
target_group.add_argument("--build", action="store_true", help="Build bitstream.")
target_group.add_argument("--load", action="store_true", help="Load bitstream.")
target_group.add_argument("--flash", action="store_true", help="Flash Bitstream.")
target_group.add_argument("--sys-clk-freq",default=27e6, help="System clock frequency.")
builder_args(parser)
soc_core_args(parser)
args = parser.parse_args()

15
litex_boards/targets/sipeed_tang_nano_9k.py
View file

@ -107,13 +107,14 @@ class BaseSoC(SoCCore):
def main():
from litex.soc.integration.soc import LiteXSoCArgumentParser
parser = LiteXSoCArgumentParser(description="LiteX SoC on Tang Nano 9K")
parser.add_argument("--build", action="store_true", help="Build bitstream.")
parser.add_argument("--load", action="store_true", help="Load bitstream.")
parser.add_argument("--flash", action="store_true", help="Flash Bitstream.")
parser.add_argument("--sys-clk-freq",default=27e6, help="System clock frequency.")
parser.add_argument("--bios-flash-offset", default="0x0", help="BIOS offset in SPI Flash.")
parser.add_argument("--with-spi-sdcard", action="store_true", help="Enable SPI-mode SDCard support.")
parser.add_argument("--prog-kit", default="openfpgaloader", help="Programmer select from Gowin/openFPGALoader.")
target_group = parser.add_argument_group(title="Target options")
target_group.add_argument("--build", action="store_true", help="Build bitstream.")
target_group.add_argument("--load", action="store_true", help="Load bitstream.")
target_group.add_argument("--flash", action="store_true", help="Flash Bitstream.")
target_group.add_argument("--sys-clk-freq",default=27e6, help="System clock frequency.")
target_group.add_argument("--bios-flash-offset", default="0x0", help="BIOS offset in SPI Flash.")
target_group.add_argument("--with-spi-sdcard", action="store_true", help="Enable SPI-mode SDCard support.")
target_group.add_argument("--prog-kit", default="openfpgaloader", help="Programmer select from Gowin/openFPGALoader.")
builder_args(parser)
soc_core_args(parser)
args = parser.parse_args()

9
litex_boards/targets/sipeed_tang_primer.py
View file

@ -64,10 +64,11 @@ class BaseSoC(SoCCore):
def main():
from litex.soc.integration.soc import LiteXSoCArgumentParser
parser = LiteXSoCArgumentParser(description="LiteX SoC on Tang Primer")
parser.add_argument("--build", action="store_true", help="Build bitstream.")
parser.add_argument("--load", action="store_true", help="Load bitstream.")
parser.add_argument("--flash", action="store_true", help="Flash Bitstream.")
parser.add_argument("--sys-clk-freq",default=24e6, help="System clock frequency.")
target_group = parser.add_argument_group(title="Target options")
target_group.add_argument("--build", action="store_true", help="Build bitstream.")
target_group.add_argument("--load", action="store_true", help="Load bitstream.")
target_group.add_argument("--flash", action="store_true", help="Flash Bitstream.")
target_group.add_argument("--sys-clk-freq",default=24e6, help="System clock frequency.")
builder_args(parser)
soc_core_args(parser)
args = parser.parse_args()

17
litex_boards/targets/sqrl_acorn.py
View file

@ -165,15 +165,16 @@ class BaseSoC(SoCCore):
def main():
from litex.soc.integration.soc import LiteXSoCArgumentParser
parser = LiteXSoCArgumentParser(description="LiteX SoC on Acorn CLE-101/215(+)")
parser.add_argument("--build", action="store_true", help="Build bitstream.")
parser.add_argument("--load", action="store_true", help="Load bitstream.")
parser.add_argument("--flash", action="store_true", help="Flash bitstream.")
parser.add_argument("--variant", default="cle-215+", help="Board variant (cle-215+, cle-215 or cle-101).")
parser.add_argument("--sys-clk-freq", default=100e6, help="System clock frequency.")
pcieopts = parser.add_mutually_exclusive_group()
target_group = parser.add_argument_group(title="Target options")
target_group.add_argument("--build", action="store_true", help="Build bitstream.")
target_group.add_argument("--load", action="store_true", help="Load bitstream.")
target_group.add_argument("--flash", action="store_true", help="Flash bitstream.")
target_group.add_argument("--variant", default="cle-215+", help="Board variant (cle-215+, cle-215 or cle-101).")
target_group.add_argument("--sys-clk-freq", default=100e6, help="System clock frequency.")
pcieopts = target_group.add_mutually_exclusive_group()
pcieopts.add_argument("--with-pcie", action="store_true", help="Enable PCIe support.")
parser.add_argument("--driver", action="store_true", help="Generate PCIe driver.")
parser.add_argument("--with-spi-sdcard", action="store_true", help="Enable SPI-mode SDCard support (requires SDCard adapter on P2).")
target_group.add_argument("--driver", action="store_true", help="Generate PCIe driver.")
target_group.add_argument("--with-spi-sdcard", action="store_true", help="Enable SPI-mode SDCard support (requires SDCard adapter on P2).")
pcieopts.add_argument("--with-sata", action="store_true", help="Enable SATA support (over PCIe2SATA).")
builder_args(parser)
soc_core_args(parser)

13
litex_boards/targets/sqrl_fk33.py
View file

@ -138,12 +138,13 @@ class BaseSoC(SoCCore):
def main():
from litex.soc.integration.soc import LiteXSoCArgumentParser
parser = LiteXSoCArgumentParser(description="LiteX SoC on FK33")
parser.add_argument("--build", action="store_true", help="Build bitstream.")
parser.add_argument("--load", action="store_true", help="Load bitstream.")
parser.add_argument("--sys-clk-freq", default=125e6, help="System clock frequency.")
parser.add_argument("--with-pcie", action="store_true", help="Enable PCIe support.")
parser.add_argument("--with-hbm", action="store_true", help="Use HBM2.")
parser.add_argument("--driver", action="store_true", help="Generate PCIe driver.")
target_group = parser.add_argument_group(title="Target options")
target_group.add_argument("--build", action="store_true", help="Build bitstream.")
target_group.add_argument("--load", action="store_true", help="Load bitstream.")
target_group.add_argument("--sys-clk-freq", default=125e6, help="System clock frequency.")
target_group.add_argument("--with-pcie", action="store_true", help="Enable PCIe support.")
target_group.add_argument("--with-hbm", action="store_true", help="Use HBM2.")
target_group.add_argument("--driver", action="store_true", help="Generate PCIe driver.")
builder_args(parser)
soc_core_args(parser)
args = parser.parse_args()

15
litex_boards/targets/sqrl_xcu1525.py
View file

@ -135,13 +135,14 @@ class BaseSoC(SoCCore):
def main():
from litex.soc.integration.soc import LiteXSoCArgumentParser
parser = LiteXSoCArgumentParser(description="LiteX SoC on XCU1525")
parser.add_argument("--build", action="store_true", help="Build bitstream.")
parser.add_argument("--load", action="store_true", help="Load bitstream.")
parser.add_argument("--sys-clk-freq", default=125e6, help="System clock frequency.")
parser.add_argument("--ddram-channel", default="0", help="DDRAM channel (0, 1, 2 or 3).")
parser.add_argument("--with-pcie", action="store_true", help="Enable PCIe support.")
parser.add_argument("--driver", action="store_true", help="Generate PCIe driver.")
parser.add_argument("--with-sata", action="store_true", help="Enable SATA support (over SFP2SATA).")
target_group = parser.add_argument_group(title="Target options")
target_group.add_argument("--build", action="store_true", help="Build bitstream.")
target_group.add_argument("--load", action="store_true", help="Load bitstream.")
target_group.add_argument("--sys-clk-freq", default=125e6, help="System clock frequency.")
target_group.add_argument("--ddram-channel", default="0", help="DDRAM channel (0, 1, 2 or 3).")
target_group.add_argument("--with-pcie", action="store_true", help="Enable PCIe support.")
target_group.add_argument("--driver", action="store_true", help="Generate PCIe driver.")
target_group.add_argument("--with-sata", action="store_true", help="Enable SATA support (over SFP2SATA).")
builder_args(parser)
soc_core_args(parser)
args = parser.parse_args()

21
litex_boards/targets/stlv7325.py
View file

@ -142,18 +142,19 @@ class BaseSoC(SoCCore):
def main():
from litex.soc.integration.soc import LiteXSoCArgumentParser
parser = LiteXSoCArgumentParser(description="LiteX SoC on STLV7325")
parser.add_argument("--build", action="store_true", help="Build bitstream.")
parser.add_argument("--load", action="store_true", help="Load bitstream.")
parser.add_argument("--sys-clk-freq", default=100e6, help="System clock frequency.")
ethopts = parser.add_mutually_exclusive_group()
target_group = parser.add_argument_group(title="Target options")
target_group.add_argument("--build", action="store_true", help="Build bitstream.")
target_group.add_argument("--load", action="store_true", help="Load bitstream.")
target_group.add_argument("--sys-clk-freq", default=100e6, help="System clock frequency.")
ethopts = target_group.add_mutually_exclusive_group()
ethopts.add_argument("--with-ethernet", action="store_true", help="Enable Ethernet support.")
ethopts.add_argument("--with-etherbone", action="store_true", help="Enable Etherbone support.")
parser.add_argument("--eth-ip", default="192.168.1.50", type=str, help="Ethernet/Etherbone IP address.")
parser.add_argument("--eth-dynamic-ip", action="store_true", help="Enable dynamic Ethernet IP addresses setting.")
parser.add_argument("--with-pcie", action="store_true", help="Enable PCIe support.")
parser.add_argument("--driver", action="store_true", help="Generate PCIe driver.")
parser.add_argument("--with-sata", action="store_true", help="Enable SATA support.")
sdopts = parser.add_mutually_exclusive_group()
target_group.add_argument("--eth-ip", default="192.168.1.50", type=str, help="Ethernet/Etherbone IP address.")
target_group.add_argument("--eth-dynamic-ip", action="store_true", help="Enable dynamic Ethernet IP addresses setting.")
target_group.add_argument("--with-pcie", action="store_true", help="Enable PCIe support.")
target_group.add_argument("--driver", action="store_true", help="Generate PCIe driver.")
target_group.add_argument("--with-sata", action="store_true", help="Enable SATA support.")
sdopts = target_group.add_mutually_exclusive_group()
sdopts.add_argument("--with-spi-sdcard", action="store_true", help="Enable SPI-mode SDCard support.")
sdopts.add_argument("--with-sdcard", action="store_true", help="Enable SDCard support.")
builder_args(parser)

9
litex_boards/targets/terasic_de0nano.py
View file

@ -92,10 +92,11 @@ class BaseSoC(SoCCore):
def main():
from litex.soc.integration.soc import LiteXSoCArgumentParser
parser = LiteXSoCArgumentParser(description="LiteX SoC on DE0-Nano")
parser.add_argument("--build", action="store_true", help="Build bitstream.")
parser.add_argument("--load", action="store_true", help="Load bitstream.")
parser.add_argument("--sys-clk-freq", default=50e6, help="System clock frequency.")
parser.add_argument("--sdram-rate", default="1:1", help="SDRAM Rate (1:1 Full Rate or 1:2 Half Rate).")
target_group = parser.add_argument_group(title="Target options")
target_group.add_argument("--build", action="store_true", help="Build bitstream.")
target_group.add_argument("--load", action="store_true", help="Load bitstream.")
target_group.add_argument("--sys-clk-freq", default=50e6, help="System clock frequency.")
target_group.add_argument("--sdram-rate", default="1:1", help="SDRAM Rate (1:1 Full Rate or 1:2 Half Rate).")
builder_args(parser)
soc_core_args(parser)
args = parser.parse_args()

9
litex_boards/targets/terasic_de10lite.py
View file

@ -88,10 +88,11 @@ class BaseSoC(SoCCore):
def main():
from litex.soc.integration.soc import LiteXSoCArgumentParser
parser = LiteXSoCArgumentParser(description="LiteX SoC on DE10-Lite")
parser.add_argument("--build", action="store_true", help="Build bitstream.")
parser.add_argument("--load", action="store_true", help="Load bitstream.")
parser.add_argument("--sys-clk-freq", default=50e6, help="System clock frequency.")
parser.add_argument("--with-video-terminal", action="store_true", help="Enable Video Terminal (VGA).")
target_group = parser.add_argument_group(title="Target options")
target_group.add_argument("--build", action="store_true", help="Build bitstream.")
target_group.add_argument("--load", action="store_true", help="Load bitstream.")
target_group.add_argument("--sys-clk-freq", default=50e6, help="System clock frequency.")
target_group.add_argument("--with-video-terminal", action="store_true", help="Enable Video Terminal (VGA).")
builder_args(parser)
soc_core_args(parser)
args = parser.parse_args()

13
litex_boards/targets/terasic_de10nano.py
View file

@ -99,12 +99,13 @@ class BaseSoC(SoCCore):
def main():
from litex.soc.integration.soc import LiteXSoCArgumentParser
parser = LiteXSoCArgumentParser(description="LiteX SoC on DE10-Nano")
parser.add_argument("--build", action="store_true", help="Build bitstream.")
parser.add_argument("--load", action="store_true", help="Load bitstream.")
parser.add_argument("--sys-clk-freq", default=50e6, help="System clock frequency.")
parser.add_argument("--with-mister-sdram", action="store_true", help="Enable SDRAM with MiSTer expansion board.")
parser.add_argument("--with-mister-video-terminal", action="store_true", help="Enable Video Terminal with Mister expansion board.")
parser.add_argument("--sdram-rate", default="1:1", help="SDRAM Rate (1:1 Full Rate or 1:2 Half Rate).")
target_group = parser.add_argument_group(title="Target options")
target_group.add_argument("--build", action="store_true", help="Build bitstream.")
target_group.add_argument("--load", action="store_true", help="Load bitstream.")
target_group.add_argument("--sys-clk-freq", default=50e6, help="System clock frequency.")
target_group.add_argument("--with-mister-sdram", action="store_true", help="Enable SDRAM with MiSTer expansion board.")
target_group.add_argument("--with-mister-video-terminal", action="store_true", help="Enable Video Terminal with Mister expansion board.")
target_group.add_argument("--sdram-rate", default="1:1", help="SDRAM Rate (1:1 Full Rate or 1:2 Half Rate).")
builder_args(parser)
soc_core_args(parser)
args = parser.parse_args()

7
litex_boards/targets/terasic_de1soc.py
View file

@ -78,9 +78,10 @@ class BaseSoC(SoCCore):
def main():
from litex.soc.integration.soc import LiteXSoCArgumentParser
parser = LiteXSoCArgumentParser(description="LiteX SoC on DE1-SoC")
parser.add_argument("--build", action="store_true", help="Build bitstream.")
parser.add_argument("--load", action="store_true", help="Load bitstream.")
parser.add_argument("--sys-clk-freq", default=50e6, help="System clock frequency.")
target_group = parser.add_argument_group(title="Target options")
target_group.add_argument("--build", action="store_true", help="Build bitstream.")
target_group.add_argument("--load", action="store_true", help="Load bitstream.")
target_group.add_argument("--sys-clk-freq", default=50e6, help="System clock frequency.")
builder_args(parser)
soc_core_args(parser)
args = parser.parse_args()

7
litex_boards/targets/terasic_de2_115.py
View file

@ -71,9 +71,10 @@ class BaseSoC(SoCCore):
def main():
from litex.soc.integration.soc import LiteXSoCArgumentParser
parser = LiteXSoCArgumentParser(description="LiteX SoC on DE2-115")
parser.add_argument("--build", action="store_true", help="Build bitstream.")
parser.add_argument("--load", action="store_true", help="Load bitstream.")
parser.add_argument("--sys-clk-freq", default=50e6, help="System clock frequency.")
target_group = parser.add_argument_group(title="Target options")
target_group.add_argument("--build", action="store_true", help="Build bitstream.")
target_group.add_argument("--load", action="store_true", help="Load bitstream.")
target_group.add_argument("--sys-clk-freq", default=50e6, help="System clock frequency.")
builder_args(parser)
soc_core_args(parser)
args = parser.parse_args()

19
litex_boards/targets/terasic_deca.py
View file

@ -119,17 +119,18 @@ class BaseSoC(SoCCore):
def main():
from litex.soc.integration.soc import LiteXSoCArgumentParser
parser = LiteXSoCArgumentParser(description="LiteX SoC on DECA")
parser.add_argument("--build", action="store_true", help="Build bitstream.")
parser.add_argument("--load", action="store_true", help="Load bitstream.")
parser.add_argument("--sys-clk-freq", default=50e6, help="System clock frequency.")
ethopts = parser.add_mutually_exclusive_group()
target_group = parser.add_argument_group(title="Target options")
target_group.add_argument("--build", action="store_true", help="Build bitstream.")
target_group.add_argument("--load", action="store_true", help="Load bitstream.")
target_group.add_argument("--sys-clk-freq", default=50e6, help="System clock frequency.")
ethopts = target_group.add_mutually_exclusive_group()
ethopts.add_argument("--with-ethernet", action="store_true", help="Enable Ethernet support.")
ethopts.add_argument("--with-etherbone", action="store_true", help="Enable Etherbone support.")
parser.add_argument("--eth-ip", default="192.168.1.50", type=str, help="Ethernet/Etherbone IP address.")
parser.add_argument("--eth-dynamic-ip", action="store_true", help="Enable dynamic Ethernet IP addresses setting.")
parser.add_argument("--with-uartbone", action="store_true", help="Enable UARTbone support.")
parser.add_argument("--with-jtagbone", action="store_true", help="Enable JTAGbone support.")
parser.add_argument("--with-video-terminal", action="store_true", help="Enable Video Terminal (VGA).")
target_group.add_argument("--eth-ip", default="192.168.1.50", type=str, help="Ethernet/Etherbone IP address.")
target_group.add_argument("--eth-dynamic-ip", action="store_true", help="Enable dynamic Ethernet IP addresses setting.")
target_group.add_argument("--with-uartbone", action="store_true", help="Enable UARTbone support.")
target_group.add_argument("--with-jtagbone", action="store_true", help="Enable JTAGbone support.")
target_group.add_argument("--with-video-terminal", action="store_true", help="Enable Video Terminal (VGA).")
builder_args(parser)
soc_core_args(parser)
args = parser.parse_args()

17
litex_boards/targets/terasic_sockit.py
View file

@ -106,14 +106,15 @@ class BaseSoC(SoCCore):
def main():
from litex.soc.integration.soc import LiteXSoCArgumentParser
parser = LiteXSoCArgumentParser(description="LiteX SoC on the Terasic SoCKit")
parser.add_argument("--single-rate-sdram", action="store_true", help="Clock SDRAM with 1x the sytem clock (instead of 2x).")
parser.add_argument("--mister-sdram-xs-v22", action="store_true", help="Use optional MiSTer SDRAM module XS v2.2 on J2 on GPIO daughter card.")
parser.add_argument("--mister-sdram-xs-v24", action="store_true", help="Use optional MiSTer SDRAM module XS v2.4 on J2 on GPIO daughter card.")
parser.add_argument("--build", action="store_true", help="Build bitstream.")
parser.add_argument("--load", action="store_true", help="Load bitstream.")
parser.add_argument("--revision", default="revd", help="Board revision (revb, revc or revd).")
parser.add_argument("--sys-clk-freq", default=50e6, help="System clock frequency.")
parser.add_argument("--with-video-terminal", action="store_true", help="Enable Video Terminal (VGA).")
target_group = parser.add_argument_group(title="Target options")
target_group.add_argument("--single-rate-sdram", action="store_true", help="Clock SDRAM with 1x the sytem clock (instead of 2x).")
target_group.add_argument("--mister-sdram-xs-v22", action="store_true", help="Use optional MiSTer SDRAM module XS v2.2 on J2 on GPIO daughter card.")
target_group.add_argument("--mister-sdram-xs-v24", action="store_true", help="Use optional MiSTer SDRAM module XS v2.4 on J2 on GPIO daughter card.")
target_group.add_argument("--build", action="store_true", help="Build bitstream.")
target_group.add_argument("--load", action="store_true", help="Load bitstream.")
target_group.add_argument("--revision", default="revd", help="Board revision (revb, revc or revd).")
target_group.add_argument("--sys-clk-freq", default=50e6, help="System clock frequency.")
target_group.add_argument("--with-video-terminal", action="store_true", help="Enable Video Terminal (VGA).")
builder_args(parser)
soc_core_args(parser)
args = parser.parse_args()

7
litex_boards/targets/tinyfpga_bx.py
View file

@ -61,9 +61,10 @@ class BaseSoC(SoCCore):
def main():
from litex.soc.integration.soc import LiteXSoCArgumentParser
parser = LiteXSoCArgumentParser(description="LiteX SoC on TinyFPGA BX")
parser.add_argument("--build", action="store_true", help="Build bitstream.")
parser.add_argument("--bios-flash-offset", default="0x50000", help="BIOS offset in SPI Flash.")
parser.add_argument("--sys-clk-freq", default=16e6, help="System clock frequency.")
target_group = parser.add_argument_group(title="Target options")
target_group.add_argument("--build", action="store_true", help="Build bitstream.")
target_group.add_argument("--bios-flash-offset", default="0x50000", help="BIOS offset in SPI Flash.")
target_group.add_argument("--sys-clk-freq", default=16e6, help="System clock frequency.")
builder_args(parser)
soc_core_args(parser)
args = parser.parse_args()

17
litex_boards/targets/trellisboard.py
View file

@ -181,18 +181,19 @@ class BaseSoC(SoCCore):
def main():
from litex.soc.integration.soc import LiteXSoCArgumentParser
parser = LiteXSoCArgumentParser(description="LiteX SoC on Trellis Board")
parser.add_argument("--build", action="store_true", help="Build bitstream.")
parser.add_argument("--load", action="store_true", help="Load bitstream.")
parser.add_argument("--toolchain", default="trellis", help="FPGA toolchain (trellis or diamond).")
parser.add_argument("--sys-clk-freq", default=75e6, help="System clock frequency.")
parser.add_argument("--with-ethernet", action="store_true", help="Enable Ethernet support.")
viopts = parser.add_mutually_exclusive_group()
target_group = parser.add_argument_group(title="Target options")
target_group.add_argument("--build", action="store_true", help="Build bitstream.")
target_group.add_argument("--load", action="store_true", help="Load bitstream.")
target_group.add_argument("--toolchain", default="trellis", help="FPGA toolchain (trellis or diamond).")
target_group.add_argument("--sys-clk-freq", default=75e6, help="System clock frequency.")
target_group.add_argument("--with-ethernet", action="store_true", help="Enable Ethernet support.")
viopts = target_group.add_mutually_exclusive_group()
viopts.add_argument("--with-video-terminal", action="store_true", help="Enable Video Terminal (HDMI).")
viopts.add_argument("--with-video-framebuffer", action="store_true", help="Enable Video Framebuffer (HDMI).")
sdopts = parser.add_mutually_exclusive_group()
sdopts = target_group.add_mutually_exclusive_group()
sdopts.add_argument("--with-spi-sdcard", action="store_true", help="Enable SPI-mode SDCard support.")
sdopts.add_argument("--with-sdcard", action="store_true", help="Enable SDCard support.")
parser.add_argument("--with-pmod-gpio", action="store_true", help="Enable GPIOs through PMOD.") # FIXME: Temporary test.
target_group.add_argument("--with-pmod-gpio", action="store_true", help="Enable GPIOs through PMOD.") # FIXME: Temporary test.
builder_args(parser)
soc_core_args(parser)
trellis_args(parser)

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