add option to use ecpprog for crosslink-nx eval board
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30180892fa
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@ -8,6 +8,7 @@
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from litex.build.generic_platform import *
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from litex.build.generic_platform import *
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from litex.build.lattice import LatticePlatform
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from litex.build.lattice import LatticePlatform
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from litex.build.lattice.programmer import LatticeProgrammer
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from litex.build.lattice.programmer import LatticeProgrammer
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from litex.build.lattice.programmer import EcpprogProgrammer
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# IOs ----------------------------------------------------------------------------------------------
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# IOs ----------------------------------------------------------------------------------------------
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@ -258,8 +259,13 @@ class Platform(LatticePlatform):
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assert device in ["LIFCL-40-9BG400C", "LIFCL-40-8BG400CES"]
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assert device in ["LIFCL-40-9BG400C", "LIFCL-40-8BG400CES"]
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LatticePlatform.__init__(self, device, _io, _connectors, toolchain=toolchain, **kwargs)
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LatticePlatform.__init__(self, device, _io, _connectors, toolchain=toolchain, **kwargs)
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def create_programmer(self, mode = "direct"):
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def create_programmer(self, mode = "direct", prog="radiant"):
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assert mode in ["direct","flash"]
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assert mode in ["direct","flash"]
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assert prog in ["radiant","ecpprog"]
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if prog == "ecpprog":
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return EcpprogProgrammer()
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xcf_template_direct = """<?xml version='1.0' encoding='utf-8' ?>
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xcf_template_direct = """<?xml version='1.0' encoding='utf-8' ?>
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<!DOCTYPE ispXCF SYSTEM "IspXCF.dtd" >
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<!DOCTYPE ispXCF SYSTEM "IspXCF.dtd" >
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@ -97,9 +97,11 @@ def main():
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target_group.add_argument("--build", action="store_true", help="Build design.")
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target_group.add_argument("--build", action="store_true", help="Build design.")
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target_group.add_argument("--load", action="store_true", help="Load bitstream.")
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target_group.add_argument("--load", action="store_true", help="Load bitstream.")
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target_group.add_argument("--toolchain", default="radiant", help="FPGA toolchain (radiant or prjoxide).")
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target_group.add_argument("--toolchain", default="radiant", help="FPGA toolchain (radiant or prjoxide).")
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target_group.add_argument("--device", default="LIFCL-40-9BG400C", help="FPGA device (LIFCL-40-9BG400C or LIFCL-40-8BG400CES).")
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target_group.add_argument("--device", default="LIFCL-40-9BG400C", help="FPGA device (LIFCL-40-9BG400C, LIFCL-40-8BG400CES, or LIFCL-40-8BG400CES2).")
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target_group.add_argument("--sys-clk-freq", default=75e6, help="System clock frequency.")
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target_group.add_argument("--sys-clk-freq", default=75e6, help="System clock frequency.")
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target_group.add_argument("--serial", default="serial", help="UART Pins (serial (requires R15 and R17 to be soldered) or serial_pmod[0-2]).")
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target_group.add_argument("--serial", default="serial", help="UART Pins (serial (requires R15 and R17 to be soldered) or serial_pmod[0-2]).")
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target_group.add_argument("--programmer", default="radiant", help="Programmer (radiant or ecpprog).")
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target_group.add_argument("--address", default=0x0, help="Flash address to program bitstream at.")
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target_group.add_argument("--prog-target", default="direct", help="Programming Target (direct or flash).")
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target_group.add_argument("--prog-target", default="direct", help="Programming Target (direct or flash).")
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builder_args(parser)
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builder_args(parser)
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soc_core_args(parser)
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soc_core_args(parser)
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@ -118,8 +120,11 @@ def main():
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builder.build(**builder_kargs)
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builder.build(**builder_kargs)
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if args.load:
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if args.load:
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prog = soc.platform.create_programmer(args.prog_target)
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prog = soc.platform.create_programmer(args.prog_target, args.programmer)
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prog.load_bitstream(builder.get_bitstream_filename(mode="sram"))
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if args.programmer == "ecpprog" and args.prog_target == "flash":
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prog.flash(address=args.address, bitstream=builder.get_bitstream_filename(mode="sram"))
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else:
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prog.load_bitstream(builder.get_bitstream_filename(mode="sram"))
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if __name__ == "__main__":
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if __name__ == "__main__":
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main()
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main()
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